Versatile Single Chip Telephone with
14 Number Repertory Dialler
SA2531AB
Key Features
VDPHV
Description
The SA2531AB is a CMOS integrated circuit
that contains all the functions needed to form
a high performance electronic telephone.
The device incorporates LD/MF repertory
dialling, melody generation, ring frequency
discrimination and a high quality line/speech
circuit.
A RAM is on chip for a 31 digit last number
redial and 14 memories each containing up to
21 digits/data.
The sliding cursor procedure makes the LNR
function easy to use under various PABX
systems.
The SAS2531AB incorporates a volume
control for the earpiece. The volume can be
controlled by the VOL key (+ 4 dB) or by the
+/– keys (+6 dB/-4 dB in 5 steps).
The versatility of the circuit is provided by on
chip programmability and a few external
components allowing easy adaptation to
different PTT requirements.
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Line/Speech circuit, LD/MF repertory
dialler and tone ringer on one 28 pin
CMOS chip
NET 4 compatible
Soft clipping to avoid harsh distortion
Line loss compensation selectable by pin
option
Operating range from 13 to 100 mA (down
to 5 mA with reduced performance)
Volume control of receive signal
Low noise
Real
or
complex
impedance
programmable
LD/MF switchable dialling
31 digits last number redial
14 memories, 4 direct/10 indirect or 10
direct
Sliding cursor protocol with comparison
Pause key for auto pause (2 sec.) or wait
function
2 flash keys, 100 ms and 600 ms
On chip MF filter (CEPT CS 203
compatible)
Ring frequency discrimination
3-tone melody generator General
Block diagram
SPEC-0436 (REV. 1)
1/23
17-08-01
SA2531AB
VDPHV
Pin Description
Pin
#
1
2
3
4
5
6
7
8
Symbol
LS
RO2
RO1
Vdd
Agnd
STB
Cl
MO
Name
Line Current Sense
Receiver Outputs
Positive Voltage Supply
Analog Ground
Side Tone Balance
Complex Impedance
Melody Output
Function
Line current sensing input
These are the outputs for driving a dynamic earpiece with
an impedance of 150 to 300 Ohms
9
LLC
Line Loss Compensation
10
11
12
13
14
15
16
17
18
19
20
21
HS/DPN
OSC
RR
C4
C3
C2
C1
R4
R3
R2
R1
FCI
Hook Switch Input and
Dial Pulse Output
Oscillator Input
Repetition Rate
This is the input for side tone cancellation
Input pin for the capacitor in the complex impedance
Pulse Density Modulated output of the melody generator
for tone ringer. At high impedance when not active
Select input pin for the line loss compensation:
LLC = OPEN NONE
LLC = LOW 20-50mA
LLC = HIGH 45-75mA
This is an I/O that is pulled high by the hook switch when
off-hook. An open drain pulls it low during break periods of
pulse dialing and flash
Oscillator pin for Xtal or ceramic resonator (3.58MHz).
Recommended: MURATA CSA 3.58MG312AM
Select input pin for repetition rate of melody for the tone
ringer
Keyboard Columns
Keyboard Rows
Frequency Comparator
Input
Signalling Mode Select
Input
This is Schmitt trigger input for ring frequency
discrimination. Disabled during off-hook
MODE=OPEN MF only
MODE=LOW LD default mode, 10pps, make/break =
40/60ms
MODE=HIGH LD default mode, 10pps, make/break =
33/66ms
Differential inputs for the microphone
This N-channel open drain output controls the external high
power shunt transistor for the modulation of the line voltage
and for shorting the line during make period of pulse
dialling
This input is used for power extraction and line current
sensing
This input is used for the receive signal
22
MODE
23
24
25
26
27
28
M1
M2
CS
Vss
LI
RI
Microphone Inputs
Current Shunt Control
Output
Negative Power Supply
Line Input
Receive Input
SPEC-0436 (REV. 1)
2/23
17-08-01
SA2531AB
Package
Available in 28 pin PDIP and SOIC
VDPHV
Pin Configurations
Keyboard Connections 1
10 direct memories (either
VOL
or
+/–
keys)
SPEC-0436
(REV. 1)
3/23
17-08-01
SA2531AB
Keyboard Connections 2
4 direct and 10 indirect memories (either
VOL
or
+/–
keys)
VDPHV
Power On Reset
The on chip power on reset circuit monitors the
supply voltage (VDD) during off-hook. When VDD
rises above approx. 1.2V, a power on reset occurs
which clears the RAM.
keep a low voltage drop at the LS pin during make
periods.
AC Impedance
The ac impedance of the circuit is set by mask
options and an external capacitor. The impedance
can be real or complex. Return loss and side tone
cancellation can be determined independent of
each other (see figure 1).
DC Conditions
The normal operating range is from 13 mA to 100
mA. Operating range with reduced performance is
from 5 mA to 13 mA (parallel operation). In the
operating range all functions are operational. At line
currents below 13 mA the SA2531 provides an
additional slope below 4.5V in order to allow
parallel operation (see figure 7). The dc
characteristic
(excluding
diode
bridge)
is
determined by the voltage at LI and the resistor R1
at line currents above 13 mA as follows:
Speech Circuit
The speech circuit consists of a transmit and a
receive path with dual soft clipping, mute, line loss
compensation and sidetone cancellation.
Transmit
The gain of the transmit path is 35 dB for 600 Ohm
and 37 dB for 1000 Ohm from M1/M2 to LS (see
test circuit figure 2). The microphone input is
differential with an input impedance of 25 kOhm.
The soft clip circuit limits the output voltage at LI to
2V
PEAK
(see figure 5 and 6). The attack time is 30
ms/6 dB and the decay time is 20ms/6dB
VLS
=
VLI
+
ILINE
×
R1
The voltage at LI is 4.5V.
During pulse dialling the speech circuit and other
part of the device not operating is in a power down
mode to save current. The CS pin is pulled to VSS
in order to turn the external shunt transistor on to
SPEC-0436 (REV. 1)
4/23
17-08-01
SA2531AB
Receive
The gain of the receive path is 2 dB for 600 Ohm
and 0 dB for 1000 Ohm (see test circuit figure 2)
with differential outputs, RO1/RO2. The receive
input is the differential signal of RI and STB. When
mute is active during dialling the gain is reduced by
> 60 dB. During DTMF dialling a MF comfort tone is
applied to the receiver. The comfort tone is the
DTMF signal with a level that is approximately -30
dB relative to the line signal.
The receive gain can be changed by pressing the
volume keys. The
VOL
key gives a +4 dB boost
and has a toggle function, i.e. repressing the key
resets the gain to default. Alternatively the
+/–
keys
can be used. The
+
key increases the gain by 6 dB
in 3 steps and the
–
key decreases the gain by 4
dB in 2 steps. The gain is reset by next off-hook.
VDPHV
mA when LLC = low and 45 to 75 mA when LLC =
high (@ R1 = 30 Ohm).
The line loss compensation is disabled when LLC =
open (see figure 3 and 4).
Dialling Functions
Valid Keys
The key scanning is enabled when HS/DPN is
pulled high and VDD is above VREF. A valid key is
detected from the keyboard by connecting the
appropriate row to the column (RON 1 kOhm). This
can be done using an n x m keyboard matrix with
single contacts. Four diodes are used to extend the
number of rows (see keyboard arrangement 1 and
2). It is also possible to connect a µ-controller to the
rows and columns.
Sidetone
A good sidetone cancellation is achieved by using
the following equation:
Mute Key
The
MUTE
key is enabled in speech mode only.
Depressing the
MUTE
key mutes the microphone
amplifier. Repressing the
MUTE
key deactivates
the mute (toggle function). Any key entry overwrites
a mute activated by the
MUTE
key and mute will be
deactivated. When privacy mute is activated, a
reminder tone is applied to the earpiece.
Z
BAL
/Z
LINE
=R5/R1
The sidetone cancellation signal is applied to the
STB input.
Dial Mode Selection
The default mode (LD or MF) can be selected by
the mode pin. When default LD mode is selected, a
temporary change to MF can be invoked by
pressing the
*
key (a metal mask option is available
whereby the MF tone generated is generated on
the first
*
key).
The circuit will revert to LD by pressing the
R
(or
R2)
key or by next onhook.
When MF mode is selected by the mode pin, the
circuit can not be changed temporary to LD but will
remain in MF.
Last Number Redial
LNR is a facility that allows re-signalling of the last
manually dialled number without keying in all the
digits again. The LNR is repeatable.
The current contents of the RAM are overwritten by
new entries.
A manually entered number is automatically stored
in the LNR RAM. The capacity of the RAM is 31
digits. If a number greater than 31 digits is entered,
the LNR facility will be inhibited (until new entries <
32 digits) and further entries will be buffered in
FIFO. Pauses can be inserted by pressing the
PAUSE
key. Post dialled digits, i.e. digits manually
entered after LNR has been invoked, are not stored
in RAM but buffered in FIFO.
Figure 1
Dual balance bridge (return loss and sidetone)
with one common ground
Side Tone is controlled along with Return Loss by a
Double Balance Bridge as shown in figure 1.
Line Loss Compensation
The line loss compensation is a pin option. When it
is activated, the transmit and receive gains are
decreased by 6 dB at line currents from 20 to 50
SPEC-0436 (REV. 1)
5/23
17-08-01
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