K7P323666M-HC300 datasheet, PDF

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K7P323666M-HC300: DescriptionLate-Write SRAM, 1MX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119; Categorystorage storage; File Size447KB，14 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7P323666M-HC300 Overview

Late-Write SRAM, 1MX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

K7P323666M-HC300 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	1.6 ns
Other features	PIPELINED ARCHITECTURE, IT CAN ALSO OPERATE AT 1.8V SUPPLY
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	37748736 bit
Memory IC Type	LATE-WRITE SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.21 mm
Maximum supply voltage (Vsup)	2.63 V
Minimum supply voltage (Vsup)	2.37 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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K7P323666M

K7P321866M

1Mx36 & 2Mx18 SRAM

32Mb M-die LW SRAM Specification

119BGA with Pb & Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure could result in loss of life or personal or physical harm, or any military

or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

-1-

Dec. 2005

Rev 1.2

K7P323666M

K7P321866M

FUNCTION DESCRIPTION

1Mx36 & 2Mx18 SRAM

The K7P323666M and K7P321866M are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of

36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are

updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one

cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second

edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this

cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Read Operation

Write(Store) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,

one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the

Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write

cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of

read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the

same as the SW signal.

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be

done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is

the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Bypass Read Operation

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance

can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM

and V

. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250

Ω

resistor will give an output buffer impedance of 50

Ω

. The allowable range of RQ is from 175

Ω

to 350

Ω

. Internal circuits evaluate and

periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-

ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the

optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.

Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance

match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum

number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-

tion by connecting ZQ to V

or V

DDQ

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

DDQ

. These

mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.

Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

-5-

Dec. 2005

Rev 1.2

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