K7P323674C
K7P321874C
1Mx36 & 2Mx18 SRAM
36Mb Late Write SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.2 February 2007
K7P323674C
K7P321874C
Document Title
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
1Mx36 & 2Mx18 SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
History
1. Initial Document
1. Change V
DD
range : from 1.8~2.5V to 1.8 or 2.5V
1. Put the data in the table of DC Characteristics, Pin Capacitance and Thermal
Resistance.
1. Change Samsung JEDEC Code in ID REGISTER DEFINITION
1. Correct typo
1. Change Max. V
REF
and V
CM
-CLK from 0.9V to 0.95V in recommended DC
operating conditions.
1. Change V
OH
in JTAG DC OPERATING CONDITION
Draft Date
Dec. 2005
Jan. 2006
Apr. 2006
Remark
Advance
Preliminary
Preliminary
Rev. 0.3
Rev. 1.0
Rev. 1.1
Jun. 2006
Aug. 2006
Dec. 2006
Preliminary
Final
Final
Rev. 1.2
Feb. 2007
Final
-2-
Rev. 1.2 February 2007
K7P323674C
K7P321874C
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations.
• 1.8 or 2.5V V
DD
/1.5V ~1.8V
DDQ
.
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
1Mx36 & 2Mx18 SRAM
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
GENERAL DESCRIPTION
The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36
bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are
updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
ORDERING INFORMATION
Org.
1Mx36
2Mx18
Maximum
Frequency
300MHz
250MHz
300MHz
250MHz
Access
Time
1.6
2.0
1.6
2.0
VDD
2.5V
1.8 / 2.5V
2.5V
1.8 / 2.5V
Part Number
K7P323674C-H(G)
1
C30
K7P323674C-H(G)
1
C25
K7P321874C-H(G)
1
C30
K7P321874C-H(G)
1
C25
Note
1 : H(G) [Package type] : G-Pb Free, H-Pb
2 : 300MHz is supported only at 2.5V V
DD.
250MHz is the maximum speed at 1.8V V
DD
-3-
Rev. 1.2 February 2007
K7P323674C
K7P321874C
FUNCTIONAL BLOCK DIAGRAM
SA[0:19] or SA[0:20]
CK
SS
SW
Latch
SWx
Register
SWx
Register
Latch
SW
Register
SW
Register
Read
Address
Register
1Mx36 & 2Mx18 SRAM
Row Decoder
1
Write
Address
Register
0
1Mx36
or
2Mx18
Array
Column Decoder
Write/Read Circuit
SWx
(x=a, b, c, d)
or (x=a, b)
0
1
Data In
Register
SS
Register
SS
Register
Data Out
Register
G
ZZ
K
K
CK
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
V
DD
V
DDQ
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Output Power Supply
Pin Name
V
REF
M
1
, M
2
G
SS
TCK
TMS
TDI
TDO
ZQ
V
SS
NC
Pin Description
HSTL Input Reference Voltage
Read Protocol Mode Pins ( M
1
=V
SS
, M
2
=V
DDQ
)
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Output Driver Impedance Control
GND
No Connection
-4-
Rev. 1.2 February 2007
K7P323674C
K7P321874C
PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7P323674C(1Mx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
SA
SA
SA
DQc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQd
SA
NC
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SWc
V
SS
V
REF
V
SS
SWd
V
SS
V
SS
V
SS
M
1
SA
TDI
4
NC
SA
V
DD
ZQ
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
SA
TCK
1Mx36 & 2Mx18 SRAM
5
SA
SA
SA
V
SS
V
SS
V
SS
SWb
V
SS
V
REF
V
SS
SWa
V
SS
V
SS
V
SS
M
2
SA
TDO
6
SA
SA
SA
DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
SA
2
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
K7P321874C(2Mx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
SA
SA
SA
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQb
SA
SA
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SWb
V
SS
V
REF
V
SS
NC
V
SS
V
SS
V
SS
M
1
SA
TDI
4
NC
SA
V
DD
ZQ
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
NC
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
NC
V
SS
V
REF
V
SS
SWa
V
SS
V
SS
V
SS
M
2
SA
TDO
6
SA
SA
SA
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
SA
SA
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
-5-
Rev. 1.2 February 2007