K7P803622B-HC250 datasheet, PDF

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K7P803622B-HC250: DescriptionStandard SRAM, 256KX36, 2.3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119; Categorystorage storage; File Size347KB，13 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7P803622B-HC250 Overview

Standard SRAM, 256KX36, 2.3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

K7P803622B-HC250 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	2.3 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	9437184 bi
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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K7P803622B

K7P801822B

Document Title

256Kx36 & 512Kx18 Synchronous Pipelined SRAM

Preliminary

256Kx36 & 512Kx18 SRAM

Revision History

Rev. No.

Rev. 0.0

Rev. 0.1

History

- Initial Document.

- Update Pin Discription. (M2=VDDQ -> M2=VDD)

- Add AC characteristics. (250Mhz, 166Mhz)

- Update DC CHARACTERISTICS

x36 : I

DD25

: TBD -> 370, I

DD20

-> 340, I

DD16

-> 320.

x18 : I

DD25

: TBD -> 360, I

DD20

-> 330, I

DD16

-> 310.

Draft Date

Jul. 2002

Oct. 2002

Remark

Preliminary

Rev. 0.2

Feb. 2003

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

-1-

Feb 2003

Rev 0.2

K7P803622B

K7P801822B

FUNCTION DESCRIPTION

Preliminary

256Kx36 & 512Kx18 SRAM

The K7P803622B and K7P801822B are 9,437,184 bit Synchronous Pipeline Mode SRAM devices. They are organized as 262,144

words by 36 bits for K7P803622B and 524,288 words by 18 bits for K7P801822B, fabricated using Samsung's advanced CMOS

technology.

Single differential PECL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising

edge of K clock, Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from

output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses

and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is

read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K

clock.

During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write Operation(Late Write)

During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the

following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and

only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the

timing of SW[a:d] is the same as the SW signal.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are

identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to

byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass

read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-

tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

. These

mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequence

The following power-up supply voltage sequence is recommended: V

, V

DDQ

, and V

. V

and V

DDQ

can be applied simulta-

neously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

-4-

Feb 2003

Rev 0.2

K7P803622B-HC250 Related Products

	K7P803622B-HC250	K7P801822B-HC250	K7P801822B-HC160	K7P803622B-HC200	K7P801822B-HC200	K7P803622B-HC160
Description	Standard SRAM, 256KX36, 2.3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX18, 2.3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX18, 3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX36, 2.5ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX18, 2.5ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 256KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, BGA-119
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,
Contacts	119	119	119	119	119	119
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknow
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	2.3 ns	2.3 ns	3 ns	2.5 ns	2.5 ns	3 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
length	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	9437184 bi	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bi
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	36	18	18	36	18	36
Number of functions	1	1	1	1	1	1
Number of terminals	119	119	119	119	119	119
word count	262144 words	524288 words	524288 words	262144 words	524288 words	262144 words
character code	256000	512000	512000	256000	512000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX36	512KX18	512KX18	256KX36	512KX18	256KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Maker	SAMSUNG	SAMSUNG	-	-	SAMSUNG	SAMSUNG

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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