DS1284/DS1286
Watchdog Timekeepers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS1284/DS1286 watchdog timekeepers are
self-contained real-time clocks, alarms, watchdog
timers, and interval timers in a 28-pin JEDEC DIP
and encapsulated DIP package. The DS1286
contains an embedded lithium energy source and a
quartz crystal, which eliminates the need for any
external circuitry. The DS1284 requires an external
quartz crystal and a V
BAT
source, which could be a
lithium battery. Data contained within 64 8-bit
registers can be read or written in the same manner
as byte-wide static RAM. Data is maintained in the
watchdog timekeeper by intelligent control circuitry
that detects the status of V
CC
and write protects
memory when V
CC
is out of tolerance. The lithium
energy source can maintain data and real time for
over 10 years in the absence of V
CC
. Watchdog
timekeeper information includes hundredths of
seconds, seconds, minutes, hours, day, date, month,
and year. The date at the end of the month is
automatically adjusted for months with fewer than
31 days, including correction for leap year. The
DS1284/DS1286 operate in either 24-hour or 12-
hour format with an AM/PM indicator. The devices
provide alarm windows and interval timing between
0.01 seconds and 99.99 seconds. The real-time
alarm provides for preset times of up to one week.
FEATURES
Keeps Track of Hundredths of Seconds,
Seconds, Minutes, Hours, Days, Date of the
Month, Months, and Years; Valid Leap Year
Compensation Up to 2100
Watchdog Timer Restarts an Out-of-Control
Processor
Alarm Function Schedules Real-Time-Related
Activities
Embedded Lithium Energy Cell Maintains
Time, Watchdog, User RAM, and Alarm
Information
Programmable Interrupts and Square-Wave
Outputs Maintain JEDEC Footprint
All Registers are Individually Addressable via
the Address and Data Bus
Accuracy is Better than ±1 Minute/Month at
+25°C (EDIP)
Greater than 10 Years of Timekeeping in the
Absence of V
CC
50 Bytes of User NV RAM
Underwriters Laboratory (UL) Recognized
-40°C to +85°C Industrial Temperature Range
Option
Pin Configurations appear at end of data sheet.
ORDERING INFORMATION
PART
TEMP RANGE
0°C to +70°C
DS1284
-40°C to +85°C
DS1284N
0°C to +70°C
DS1284Q
0°C to +70°C
DS1284Q+
0°C to +70°C
DS1284Q/T&R
0°C to +70°C
DS1284Q+T&R
-40°C to +85°C
DS1284QN
-40°C to +85°C
DS1284QN+
-40°C to +85°C
DS1284QN/T&R
-40°C to +85°C
DS1284QN+T&R
0°C to +70°C
DS1286
-40°C to +85°C
DS1286I
-40°C to +85°C
DS1286I+
+
Denotes a lead-free/RoHS-compliant package.
VOLTAGE (V)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
PIN-PACKAGE
28 DIP (600 mils)
28 DIP (600 mils)
28 PLCC
28 PLCC
28 PLCC/Tape and Reel
28 PLCC/Tape and Reel
28 PLCC
28 PLCC
28 PLCC/Tape and Reel
28 PLCC/Tape and Reel
28 EDIP (720 mils)
28 EDIP (720 mils)
28 EDIP (720 mils)
TOP MARK*
DS1284
DS1284 N
DS1284Q
DS1284Q
DS1284Q
DS1284Q
DS1284QN
DS1284QN
DS1284QN
DS1284QN
DS1286
DS1286 IND
DS1286 IND
* A “+” anywhere on the top mark indicates a lead-free package.
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REV: 032406
DS1284/DS1286
OPERATION—READ REGISTERS
The DS1284/DS1286 execute a read cycle whenever
WE
(write enable) is inactive (high) and
CE
(chip
enable) and
OE
(output enable) are active (low). The unique address specified by the six address inputs
(A0–A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight data
output drivers within t
ACC
(access time) after the last address input signal is stable, provided that
CE
and
OE
access times are also satisfied. If
OE
and
CE
access times are not satisfied, then data access must be
measured from the latter occurring signal (CE or
OE)
and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE
rather than address access.
OPERATION—WRITE REGISTERS
The DS1284/DS1286 are in the write mode whenever the
WE
and
CE
signals are in the active-low state
after the address inputs are stable. The latter occurring falling edge of
CE
or
WE
determines the start of
the write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE.
All address inputs
must be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery
state (t
WR
) before another cycle can be initiated. Data must be valid on the data bus with sufficient data
setup (t
DS
) and data hold time (t
DH
) with respect to the earlier rising edge of
CE
or
WE.
The
OE
control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output
bus has been enabled (CE and
OE
active), then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION
The watchdog timekeeper provides full functional capability when V
CC
is greater than V
TP
. Data is
maintained in the absence of V
CC
without any additional support circuitry. The DS1284/DS1286
constantly monitor V
CC
. Should the supply voltage decay, the watchdog timekeeper automatically write
protects itself, and all inputs to the registers become “don’t care.” Both
INTA
and
INTB
(INTB) are
open-drain outputs. The two interrupts and the internal clock continue to run regardless of the level of
V
CC
. However, it is important to ensure that the pullup resistors used with the interrupt pins are never
pulled up to a value greater than V
CC
+ 0.3V. As V
CC
falls below the battery voltage, a power-switching
circuit turns on the lithium energy source to maintain the clock and timer data functionality. Also ensure
that during this time (battery-backup mode), the voltage present at
INTA
and
INTB
(INTB) never
exceeds the battery voltage. If the active-high mode is selected for
INTB
(INTB), this pin only goes high
in the presence of V
CC
. During power-up, when V
CC
rises above approximately 3.0V, the power-switching
circuit connects external V
CC
and disconnects the V
BAT
energy source. Normal operation can resume after
V
CC
exceeds V
TP
for t
REC
.
WATCHDOG TIMEKEEPER REGISTERS
The watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog,
control, and data information. The clock, calendar, alarm, and watchdog registers are memory locations
that contain external (user-accessible) and internal copies of the data. The external copies are independent
of internal functions, except that they are updated periodically by the simultaneous transfer of the
incremented internal copy (see Figure 1). The command register bits are affected by both internal and
external functions. This register is discussed later. The 50 bytes of RAM registers can only be accessed
from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day and date
information (see Figure 2). Time-of-day information is stored in binary-coded decimal (BCD). Registers
3, 5, and 7 contain the time-of-day alarm information. Time-of-day alarm information is stored in BCD.
Register B is the command register and information in this register is binary. Registers C and D are the
watchdog alarm registers and information stored in these two registers is in BCD. Registers E to 3F are
user bytes and can be used to contain data at the user’s discretion.
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DS1284/DS1286
PIN DESCRIPTION
DIP
1
PIN
EDIP
1
PLCC
1
NAME
INTA
FUNCTION
Active-Low Interrupt Output A. This open-drain pin requires a
pullup resistor for proper operation.
Connections for Standard 32.768kHz Quartz Crystal. The internal
oscillator circuitry is designed for operation with a crystal having
a specified load capacitance (C
L
) of 6pF. The crystal is connected
directly to the X1 and X2 pins. There is no need for external
capacitors or resistors. For more information on crystal selection
and crystal layout considerations, refer to
Application Note 58:
Crystal Considerations with Dallas Real Time Clocks.
No Connection
Address Inputs
Data Input/Output
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Square-Wave Output. Push-pull output. High impedance when
V
CC
is below V
TP
.
Active-Low RAM Clear. Used to clear (set to logic 1) all 50
bytes of user NV RAM, but does not affect the registers
involved with time, alarm, and watchdog functions. To clear the
RAM,
RCLR
must be forced to an input logic 0 (-0.3V to
+0.8V) during battery-backup mode when V
CC
is not applied.
The
RCLR
function is designed to be used via human interface
(shorting to ground or by switch) and not be driven with external
buffers. This pin is internally pulled up and should be left
floating when not in use.
Input for Any Standard 3V Lithium Cell or Other Energy
Source. Input voltage must be held between the minimum and
maximum limits for proper operation. The supply should be
connected directly to the V
BAT
pin. A diode must not be placed
in series with the battery to the V
BAT
pin. Furthermore, a diode is
not necessary because reverse charging current-protection
circuitry is provided internal to the device and has passed the
requirements of Underwriters Laboratories for UL listing. This
pin should be grounded but can be left floating.
Active-Low (Active-High) Interrupt Output B. When the active-
high state is selected (IBH = 1), an open-drain pullup transistor
connected to V
CC
sources current when the output is active.
When the active-low state is selected (IBH = 0), an open-drain
pulldown transistor connected to ground sinks current when the
output is active. If active-high output operation is selected, a
pulldown resistor is required for proper operation. When active-
low output operation is selected, a pullup resistor is required for
proper operation.
Active-Low Write-Enable Input
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2, 3
—
2, 3
X1, X2
4
5–10
11, 12,
13, 15,
16–19
14, 21
20
22
23
2, 3, 4,
21, 24,
25
5–10
11, 12,
13, 15,
16–19
14
20
22
23
4
5–10
11, 12,
13, 15,
16–19
14, 21
20
22
23
N.C.
A5–A0
DQ0, DQ1,
DQ2, DQ3,
DQ4–DQ7
GND
CE
OE
SQW
24
—
24
RCLR
25
—
25
V
BAT
26
26
26
INTB
(INTB)
27
27
27
WE
DS1284/DS1286
DIP
PIN
EDIP
PLCC
NAME
FUNCTION
Primary Power-Supply Input. When voltage is applied within
normal limits, the device is fully accessible and data can be
written and read. When a backup supply is connected to the
device and V
CC
is below V
TP
, read and writes are inhibited.
However, the timekeeping function continues unaffected by the
lower input voltage.
28
28
28
V
CC
Figure 1. Block Diagram
V
CC
X1
X2
DS1286
only
÷
4
Internal Registers
Address Decode and Control
External Registers,
clock, calendar,
time of day alarm
Command
Register
100Hz
User RAM
50 Bytes
Internal Counters
External
Registers
Watchdog Alarm
Internal Counters
100Hz
Internal Registers
External
Registers
Hundredths of
Seconds
Update seconds through
years and check time of
day alarm
TD INT
Swap
pins
WD INT
V
CC
IBH
P
N
V
BAT
Oscillator
÷
8
÷
40.96
÷
40.96
PF delay
÷
10
Power
Switch
GND
DS1286 only
1024Hz
SQW
INTA
A0-A5
CE
OE
WE
INTB/
(INTB)
N
DS1284/DS1286
Data I/O Buffers
DQ0–DQ7
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DS1284/DS1286
HUNDREDTHS-OF-SECONDS GENERATOR
The hundredths-of-seconds generator circuit shown in the
Block Diagram
(Figure 1) is a state machine
that divides the incoming frequency (4096Hz) by 41 for 24 cycles and 40 for 1 cycle. This produces a
100Hz output that is slightly off during the short term, and is exactly correct every 250ms. The divide
ratio is given by:
Ratio = [41 x 24 + 40 x 1] / 25 = 40.96
Thus, the long-term average frequency output is exactly 100Hz.
Figure 2. Watchdog Timekeeper Registers
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