BX80526F733256E datasheet, PDF

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BX80526F733256E: DescriptionMicroprocessor, 32-Bit, 733MHz, CMOS, PPGA370, FCPGA2-370; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，94 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80526F733256E Overview

Microprocessor, 32-Bit, 733MHz, CMOS, PPGA370, FCPGA2-370

BX80526F733256E Parametric

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	PGA,
Contacts	370
Reach Compliance Code	unknow
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	733 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PPGA-P370
length	49.53 mm
low power mode	YES
Number of terminals	370
Package body material	PLASTIC/EPOXY
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2.089 mm
speed	733 MHz
Minimum supply voltage	1.65 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Intel

Pentium

III Processor with 512KB L2

Cache at 1.13GHz to 1.40GHz

Datasheet

Product Features

Available at 1.13, 1.26 and 1.40GHz

512KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC))

Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and

dedicated internal high-speed cache bus

Internet Streaming SIMD Extensions for

enhanced video, sound and 3D performance

Binary compatible with applications running

on previous members of the Intel

microprocessor line

Dynamic execution micro architecture

Power Management capabilities

— System Management mode

— Multiple low-power states

Optimized for 32-bit applications running on

advanced 32-bit operating systems

Flip Chip Pin Grid Array (FC-PGA2) packaging

technology; FC-PGA2 processors deliver high

performance with improved handling protection

and socketability

Integrated high performance 16KB instruction

and 16KB data, nonblocking, level one cache

512KB Integrated Full Speed level two cache

allows for low latency on read/store operations

Quad Quadword Wide (256 bit) cache data bus

provides extremely high throughput on read/

store operations.

8-way cache associativity provides improved

cache hit rate on reads/store operations.

Error-correcting code for System Bus data

Data Prefetch Logic

The Pentium

III

processor with 512KB L2 Cache is designed for high-performance workstations and

servers. It is binary compatible with previous Intel architecture processors. The Pentium

III

processor

with 512KB L2 Cache provides great performance for applications running on advanced operating

systems such as Windows* 98, Windows* NT, Windows* 2000, Windows* Me and Linux. This is

achieved by integrating the best attributes of Intel processors—the dynamic execution, Dual

Independent Bus architecture plus Intel

MMX™ technology and Internet Streaming SIMD

Extensions—bringing a new level of performance for systems buyers. The Pentium

III

processor with

512KB L2 Cache extends the power of the Pentium

II processor with performance headroom for

business media, communication and internet capabilities. Systems based on the Pentium

III

processor

with 512KB L2 Cache also include the latest features to simplify system management and lower the

cost of ownership for large and small business environments. The Pentium

III

processor with 512KB

L2 Cache offers great performance for today’s and tomorrow’s applications.

FC-PGA2 370 Package

June 2002

Order Number:

249657-005

Intel

Pentium

III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Pentium

III Processor with 512KB L2 Cache may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

States or other countries.

* Other names and brands may be claimed as the property of others.

Datasheet

Intel

Pentium

III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz

Contents

1.0

Introduction

.................................................................................................................. 1

1.1

Terminology........................................................................................................... 2

1.1.1 Package and Processor Terminology ...................................................... 2

1.1.2 Processor Naming Convention.................................................................3

Related Documents............................................................................................... 4

Revision History .................................................................................................... 4

Processor System Bus and V

REF ............................................................................................ 5

Clock Control and Low Power States.................................................................... 6

2.2.1 Normal State—State 1 ............................................................................. 7

2.2.2 AutoHALT Powerdown State—State 2..................................................... 7

2.2.3 Stop-Grant State—State 3 .......................................................................8

2.2.4 HALT/Grant Snoop State—State 4 .......................................................... 8

2.2.5 Sleep State—State 5................................................................................ 8

2.2.6 Deep Sleep State—State 6 ...................................................................... 9

2.2.7 Clock Control............................................................................................ 9

Power and Ground Pins ......................................................................................10

2.3.1 Phase Lock Loop (PLL) Power...............................................................10

Decoupling Guidelines ........................................................................................11

2.4.1 Processor VCC

CORE

Decoupling............................................................11

Processor System Bus Clock and Processor Clocking .......................................11

Voltage Identification ...........................................................................................12

Processor System Bus Unused Pins...................................................................15

Processor System Bus Signal Groups ................................................................15

2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................16

2.8.2 System Bus Frequency Select Signals ..................................................17

............................................................................................... Maximum Ratings18

Processor Voltage Level Specifications ..............................................................18

AGTL System Bus Specifications........................................................................24

System Bus Timing Specifications ......................................................................24

BCLK/BCLK# & PICCLK Signal Quality Specifications and Measurement Guide-

lines37

AGTL Signal Quality Specifications and Measurement Guidelines.....................38

AGTL Signal Quality Specifications and Measurement Guidelines.....................39

3.3.1 Overshoot/Undershoot Guidelines .........................................................39

3.3.2 Overshoot/Undershoot Magnitude .........................................................40

3.3.3 Overshoot/Undershoot Pulse Duration...................................................40

3.3.4 Activity Factor .........................................................................................40

3.3.5 Reading Overshoot/Undershoot Specification Tables............................41

3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications

Non-AGTL Signal Quality Specifications and Measurement Guidelines.............44

3.4.1 Overshoot/Undershoot Guidelines .........................................................44

3.4.2 Ringback Specification ...........................................................................45

3.4.3 Settling Limit Guideline...........................................................................45

1.2

1.3

2.0

Electrical Specifications

.......................................................................................... 5

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

3.0

Signal Quality Specifications

..............................................................................37

3.1

3.2

3.3

3.4

Datasheet

Intel

Pentium

III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz

4.0

Thermal Specifications and Design Considerations

................................. 47

4.1

Thermal Specifications........................................................................................ 47

4.1.1 THERMTRIP# Requirement................................................................... 47

4.1.2 Thermal Diode........................................................................................ 48

Thermal Metrology .............................................................................................. 48

FC-PGA2 Mechanical Specifications .................................................................. 49

Recommended Mechanical Keep-Out Zones ..................................................... 52

Processor Markings ............................................................................................ 53

Processor Signal Listing...................................................................................... 54

Mechanical Specifications................................................................................... 71

6.1.1 Mechanical Specifications for the FC-PGA2 Package ........................... 71

6.1.2 Boxed Processor Heatsink Weight......................................................... 72

Thermal Specifications........................................................................................ 73

6.2.1 Boxed Processor Cooling Requirements ............................................... 73

6.2.2 Boxed Processor Thermal Cooling Solution Clip ................................... 73

Electrical Requirements for the Boxed Intel® Pentium® III Processor with 512KB

L2 Cache74

6.3.1 Electrical Requirements ......................................................................... 74

Alphabetical Signals Reference .......................................................................... 76

Signal Summaries ............................................................................................... 84

4.2

5.0

Mechanical Specifications

................................................................................... 49

5.1

5.2

5.3

5.4

6.0

Boxed Processor Specifications

....................................................................... 70

6.1

6.2

6.3

7.0

Processor Signal Description

............................................................................. 76

7.1

7.2

Datasheet

Intel

Pentium

III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz

List of Figures

Integrated Heat Spreader (IHS) ............................................................................ 1

AGTL Bus Topology .............................................................................................. 6

Stop Clock State Machine ..................................................................................... 7

PLL Filter Specification........................................................................................10

Differential/Single-Ended Clocking Example.......................................................12

Power Good and Bus Select Interconnect Diagram .....................................14

BSEL[1:0] Example for a System Design............................................................17

Vcc Static & Transient Tolerance ........................................................................22

Clock Waveform ..................................................................................................32

BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform ..............................32

System Bus Valid Delay Timings ........................................................................33

System Bus Setup and Hold Timings..................................................................33

System Bus Reset and Configuration Timings....................................................34

Platform Power-On Sequence and Timings ........................................................34

Test Timings (TAP Connection) ..........................................................................35

Power-On Reset and Configuration Timings.......................................................35

Test Reset Timings .............................................................................................36

BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins ...........38

Low to High AGTL Receiver Ringback Tolerance...............................................39

Maximum Acceptable AGTL Overshoot/Undershoot Waveform .........................43

Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback 1 ....................44

Package Dimensions...........................................................................................50

FC-PGA2 IHS Flatness Specification..................................................................52

Volumetric Keep-Out ...........................................................................................52

Component Keep-Out .........................................................................................53

Top Side Processor Markings .............................................................................53

Intel® Pentium® III processor with 512KB L2 Cache Pinout ..............................54

Conceptual Boxed Intel® Pentium® III Processor with 512KB L2 Cache for the

PGA370 Socket70

Comparison between FC-PGA and FC-PGA2 package......................................71

Dimensions of Mechanical Step Feature in Heatsink Base.................................72

Side View of Space Requirements for the Boxed Processor ..............................72

Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor with

512KB L2 Cache Fan Heatsinks in the PGA370 Socket73

Boxed Processor Fan Heatsink Power Cable Connector Description.................74

Motherboard Power Header Placement Relative to the Boxed Intel® Pentium® III

Processor with 512KB L2 Cache75

Datasheet

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