EM620FV16B datasheet, PDF - EEWORLD Datasheet

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EM620FV16B: Description128K x16 bit Low Power and Low Voltage Full CMOS Static RAM; File Size432KB，11 Pages; ManufacturerETC2

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EM620FV16B Overview

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM

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EM620FV16B Series

Low Power, 128Kx16 SRAM

Document Title

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

0.0

0.1

0.2

History

Initial Draft

0.1 Revision

0.2 Revision

Remove BYTE option information

Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),

tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),

tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),

ICC(2mA to 3mA), ICC1(2mA to 3mA)

level change from 2.0V to 2.2V

Draft Date

June 7, 2007

June 15, 2007

July 2, 2007

Remark

0.3

0.3 Revision

Aug. 16, 2007

4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea

Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com

Emerging Memory & Logic Solutions Inc.

Zip Code : 690-719

The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your

questions about device. If you have any questions, please contact the EMLSI office.

EM620FV16B Series

Low Power, 128Kx16 SRAM

FUNCTIONAL SPECIFICATIONS

There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively.

Each die and wafer support dedicated characteristics and probe the electrical parameters within their specifications. Followings are

brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters

are not guaranteed at bare die and wafer.

−

C1 LEVEL DIE OR W1 LEVEL WAFER

The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C tem-

perature, which called

‘Hot

DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer

to qualification report for device reliability and package level datasheets for electrical parameters.

−

C2 LEVEL DIE OR W2 LEVEL WAFER

The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2

die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are

tested at 70°C temperature, which called

‘Hot

DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted

including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical param-

eters.

C2 level die and W2 level wafer probe following AC parameter.

−

tRC, tAA, tCO

−

tWC, tCW

PACKAGING

Individual device will be packed in anti-static trays.

−

Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle

pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents

rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic

discharge. The chip carriers will be labeled with the following information :

−

EMLSI wafer lot number

−

EMLSI part number

−

Quantity

−

Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is

consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each

pack has typically 24 wafers and then several packs are put into larger box depending on amounts of wafers.

Bond Pad #1 at Top

Die orientation in chip carriers

STORAGE AND HANDLING

EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe

environment when inspection and assembly.

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