EM620FV8B Series
Low Power, 256Kx8 SRAM
Document Title
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
0.1
0.2
0.3
History
Initial Draft
0.1 Revision
0.2 Revision
0.3 Revision
Remove BYTE option information
Remove UB, LB information
Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),
tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),
tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),
ICC(2mA to 3mA), ICC1(2mA to 3mA)
V
IH
level change from 2.0V to 2.2V
Draft Date
June 7, 2007
June 15, 2007
June 21, 2007
July 2, 2007
Remark
0.4
0.4 Revision
Aug. 16, 2007
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM620FV8B Series
Low Power, 256Kx8 SRAM
256K x8 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES
- Process Technology : 0.15µm Full CMOS
-
Organization :256K x8
-
Power Supply Voltage
=> EM620FV8B : 2.7~3.6V
-
Low Data Retention Voltage : 1.5V
-
Three state output and TTL Compatible
-
Packaged product designed for 45/55/70ns
GENERAL PHYSICAL SPECIFICATIONS
-
Backside die surface of polished bare silicon
-
Typical Die Thickness = 725um +/-15um
-
Typical top-level metallization :
=> Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms
-
Topside Passivation :
=> Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms
-
Wafer diameter : 8 inch
OPTIONS
- C1/W1 : DC Probed Die/Wafer @ Hot Temp
- C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp
1
56
29
EM620FV8B (Dual C/S)
+
(0.0)
EMLSI LOGO
28
y
x
Pre-charge Circuit
PAD DESCRIPTIONS
Name
CS1,CS2
OE
WE
A0~A17
I/O0~I/O7
Function
Chip select inputs
Output Enable input
Write Enable input
Address Inputs
Data Inputs/Outputs
Name
Vcc
Vss
NC
Function
Power Supply
Ground
No Connection
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
V
CC
Row Select
V
SS
Memory Array
1024 x 2048
I/O0 ~ I/O7
Data
Cont
I/O Circuit
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
WE
OE
CS1
CS2
Control Logic
BONDING INSTRUCTIONS
The 2M full CMOS SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates.
EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity.
2
EM620FV8B Series
Low Power, 256Kx8 SRAM
FUNCTIONAL SPECIFICATIONS
There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively.
Each die and wafer support dedicated characteristics and probe the electrical parameters within their specifications. Followings are
brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters
are not guaranteed at bare die and wafer.
−
C1 LEVEL DIE OR W1 LEVEL WAFER
The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C tem-
perature, which called
‘Hot
DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer
to qualification report for device reliability and package level datasheets for electrical parameters.
−
C2 LEVEL DIE OR W2 LEVEL WAFER
The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2
die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are
tested at 70°C temperature, which called
‘Hot
DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted
including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical param-
eters.
C2 level die and W2 level wafer probe following AC parameter.
−
tRC, tAA, tCO
−
tWC, tCW
PACKAGING
Individual device will be packed in anti-static trays.
−
Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle
pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents
rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic
discharge. The chip carriers will be labeled with the following information :
−
EMLSI wafer lot number
−
EMLSI part number
−
Quantity
−
Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is
consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each
pack has typically 24 wafers and then several packs are put into larger box depending on amounts of wafers.
Bond Pad #1 at Top
Die orientation in chip carriers
STORAGE AND HANDLING
EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe
environment when inspection and assembly.
3
EM620FV8B Series
Low Power, 256Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
A
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
-40 to 85
Unit
V
V
W
o
C
*
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
H
X
X
L
L
L
L
CS2
X
L
X
H
H
H
H
OE
X
X
X
H
H
L
X
WE
X
X
X
H
H
H
L
I/O
0-7
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data In
Mode
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Read
Write
Power
Stand by
Stand by
Stand by
Active
Active
Active
Active
Note: X means don’t care. (Must be low or high state)
4
EM620FV8B Series
Low Power, 256Kx8 SRAM
RECOMMENDED DC OPERATING CONDITIONS
1)
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
1.
2.
3.
4.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
2.7
0
2.2
-0.2
3)
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.2
2)
0.6
Unit
V
V
V
V
TA= -40 to 85
o
C, otherwise specified
Overshoot: V
CC
+2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested
.
CAPACITANCE
1)
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
V
OL
V
OH
I
SB
V
IN
=V
SS
to V
CC
CS1=V
IH
or CS2=V
IL
or OE=V
IH
or WE=V
IL
V
IO
=V
SS
to V
CC
I
IO
=0mA, CS1=V
IL
, CS2=WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS1<0.2V, CS2>V
CC
-0.2V,
V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS1=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS1>V
CC
-0.2V, CS2>V
CC
-0.2V (CS controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~V
CC
(Typ. condition : V
CC
=3.3V @ 25
o
C)
(Max. condition : V
CC
=3.6V @ 85
o
C)
Test Conditions
Min
-1
-1
-
-
45ns
55ns
70ns
-
-
-
-
2.4
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
3
3
35
30
25
0.4
-
0.3
Unit
uA
uA
mA
mA
mA
Output low voltage
Output high voltage
Standby Current (TTL)
V
V
mA
Standby Current (CMOS)
I
SB1
LF
-
1
1)
10
uA
NOTES
1. Typical values are measured at Vcc=3.3V, T
A
=
25
o
C and not 100% tested.
5
51mcu
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