Section I. Stratix II Device
Family Data Sheet
This section provides the data sheet specifications for Stratix
®
II devices.
This section contains feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
■
■
■
■
■
■
Chapter 1, Introduction
Chapter 2, Stratix II Architecture
Chapter 3, Configuration & Testing
Chapter 4, Hot Socketing & Power-On Reset
Chapter 5, DC & Switching Characteristics
Chapter 6, Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Altera Corporation
Section I–1
Stratix II Device Family Data Sheet
Stratix II Device Handbook, Volume 1
Section I–2
Altera Corporation
1. Introduction
SII51001-4.2
Introduction
The Stratix
®
II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
The Stratix II family offers the following features:
■
■
Features
■
■
■
■
■
■
15,600 to 179,400 equivalent LEs; see
Table 1–1
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
Altera Corporation
May 2007
1–1
Features
■
■
■
■
■
■
■
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
ALMs
Adaptive look-up tables (ALUTs)
(1)
Equivalent LEs
(2)
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
18-bit × 18-bit multipliers
(3)
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
Notes to
Table 1–1:
(1)
(2)
(3)
One ALM contains two ALUTs. The ALUT is the cell used in the Quartus
®
II software for logic synthesis.
This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
These multipliers are implemented using the DSP blocks.
EP2S15
6,240
12,480
15,600
104
78
0
419,328
12
48
2
4
366
EP2S30
13,552
27,104
33,880
202
144
1
1,369,728
16
64
2
4
500
EP2S60
24,176
48,352
60,440
329
255
2
2,544,192
36
144
4
8
718
EP2S90
36,384
72,768
90,960
488
408
4
4,520,488
48
192
4
8
902
EP2S130
53,016
106,032
132,540
699
609
6
6,747,840
63
252
4
8
1,126
EP2S180
71,760
143,520
179,400
930
768
9
9,383,040
96
384
4
8
1,170
1–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Introduction
Stratix II devices are available in space-saving FineLine BGA
®
packages
(see
Tables 1–2
and
1–3).
Table 1–2. Stratix II Package Options & I/O Pin Counts
484-Pin
FineLine BGA
342
342
334
308
Notes (1), (2)
780-Pin
FineLine
BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Device
484-Pin
Hybrid
FineLine
BGA
672-Pin
FineLine
BGA
366
500
492
EP2S15
EP2S30
EP2S60
(3)
EP2S90
(3)
EP2S130
(3)
EP2S180
(3)
Notes to
Table 1–2:
(1)
(2)
(3)
718
534
534
758
742
742
902
1,126
1,170
All I/O pin counts include eight dedicated clock input pins (clk1p,
clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p,
and
clk11n)
that can be used for data inputs.
The Quartus II software I/O pin counts include one additional pin,
PLL_ENA
, which is not available as general-
purpose I/O pins. The
PLL_ENA
pin can only be used to enable the PLLs within the device.
The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n,
FPLL8CLKp/n, FPLL9CLKp/n,
and
FPLL10CLKp/n)
that can be used for data inputs.
Table 1–3. Stratix II FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
484 Pin
1.00
529
23 × 23
484-Pin
Hybrid
1.00
729
27 × 27
672 Pin
1.00
729
27 × 27
780 Pin
1.00
841
29 × 29
1,020 Pin
1.00
1,089
33 × 33
1,508 Pin
1.00
1,600
40 × 40
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
Altera Corporation
May 2007
1–3
Stratix II Device Handbook, Volume 1
京公网安备 11010802033920号
EEWORLD
