BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616UV2019
• Wide Vcc operation voltage :
C-grade: 1.8V~3.6V
I-grade: 1.9V~3.6V
(Vcc_min.=1.65V at 25
o
C)
• Ultra low power consumption :
Vcc = 2.0V
C-grade: 8mA (Max.) operating current
I -grade: 10mA (Max.) operating current
0.20uA (Typ.) CMOS standby current
Vcc = 3.0V
C-grade: 11mA (Max.) operating current
I -grade: 13mA (Max.) operating current
0.30uA (Typ.) CMOS standby current
• High speed access time :
-85
85ns (Max.)
-10
100ns (Max.)
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
• Data retention supply voltage as low as 1.0V
DESCRIPTION
The BS616UV2019 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA at 2.0V /25
o
C and maximum access time of 85ns at 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616UV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2019 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616UV2019DC
BS616UV2019TC
BS616UV2019AC
BS616UV2019DI
BS616UV2019TI
BS616UV2019AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
C-grade:1.8~3.6V
I-grade:1.9~3.6V
( I
CCSB1
, Max )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
PKG TYPE
DICE
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
+0
O
C to +70
O
C
-40
O
C to +85
O
C
1.8V ~3.6V
1.9V ~ 3.6V
85/100
85/100
3.0uA
2.0uA
11mA
8mA
10mA
5.0uA
3.0uA
13mA
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
48
47
46
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
Address
Input
Buffer
9
10
13
16
17
20
Row
Decoder
1024
Memory Array
1024 x 2048
BS616UV2019TC
BS616UV2019TI
37
27
24
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
N.C.
2
OE
UB
D10
D11
D12
D13
N.C.
A8
3
A0
A3
A5
N.C.
N.C.
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
N.C.
D0
D2
VCC
VSS
D6
D7
N.C.
25
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE2 ,CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
48-ball BGA top view
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616UV2019
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS616UV2019
Name
A0-A16 Address Input
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
Function
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
(48B BGA
ignore
CE2
pin)
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE
H
X
X
L
L
CE2
(1)
X
L
X
H
H
WE
X
X
X
H
H
OE
X
X
X
H
L
LB
X
X
H
X
L
H
L
L
Write
L
H
L
X
H
L
1. 48B BGA ignore CE2 condition.
UB
X
X
H
X
L
L
H
L
L
H
D0~D7
High Z
High Z
High Z
High Z
Dout
High Z
Dout
Din
X
Din
D8~D15
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
R0201-BS616UV2019
2
Revision 1.1
Jan.
2004
BSI
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
BS616UV2019
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
1.8V ~ 3.6V
1.9V ~ 3.6V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
(5)
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current
TTL
TEST CONDITIONS
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
MIN. TYP.
-0.3
1.4
2.0
--
--
--
Vcc-0.2
2.4
--
--
--
--
--
--
(6)
(1)
MAX.
0.6
0.8
Vcc+0.3
1
1
0.2
0.4
--
10
13
0.1
0.5
3.0
5.0
UNITS
V
V
uA
uA
V
V
mA
mA
uA
--
--
--
--
--
--
--
--
--
--
0.20
0.30
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or CE2
(4)
= V
IL
,
or OE = V
IH
, V
I/O
= 0V to V
CC
Vcc=2.0V
I
OL
= 0.1mA ; Vcc=Max
Vcc=3.0V
I
OL
= 2.0mA ; Vcc=Max
I
OH
= -0.1mA ; Vcc=Min
I
OH
= -1.0mA ; Vcc=Min
CE = V
IL
CE2 = V
IH
(3)
(4)
,I
DQ
= 0mA, F = Fmax
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
CE = V
IH
(4)
, I
DQ
= 0mA
or CE2 = V
IL
CE
≧
Vcc-0.2V, or CE2
≦
0.2V,
(4)
Standby Current CMOS
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
1.
Typical characteristics are at T
A
= 25
o
C.
2.
These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3.
Fmax = 1/t
RC
.
4.
48B BGA ignore CE2 condition.
5.I
cc
s
B1
is 2.0uA/3.0uA at Vcc=2.0V/3.0V and T
A
=70
o
C.
6.
V
IL
= -1.5V for pulse width less than 30ns
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
(4)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE
≧
Vcc - 0.2V or CE2
≦
0.2V
(3)
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V or CE2
≦
0.2V
(3)
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.0
--
0
T
RC (2)
TYP.
(1)
--
0.1
--
--
MAX.
--
1.0
--
--
UNITS
V
uA
ns
ns
1.
Vcc = 1.0V, T
A
= + 25
O
C
3.
48B BGA ignore CE2 condition.
R0201-BS616UV2019
2.
t
RC
= Read Cycle Time
4.
Icc
DR
is 0.7uA at T
A
=70
o
C.
3
Revision 1.1
Jan.
2004
BSI
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616UV2019
V
DR
≥
1.0V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
( 48B BGA ignore CE2 condition)
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 100ns
(Vcc = 1.9~3.6V)
CYCLE TIME : 85ns
(Vcc = 1.9~3.6V)
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1 , 2
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
(1)
100
--
(CE,CE2)
(LB,UB)
(CE,CE2)
(LB,UB)
(CE,CE2)
(LB,UB)
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
--
--
40
40
35
--
85
--
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
40
40
--
--
--
35
35
30
--
NOTE :
1. t
BA
is 50ns/40ns (@speed=100ns/85ns) with address toggle. ; t
BA
is 100ns/85ns (@speed=100ns/85ns) without address toggle.
R0201-BS616UV2019
4
Revision 1.1
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616UV2019
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE2
t
ACS2(6)
t
ACS1
CE
t
D
OUT
(5,6)
CLZ
t
CHZ
(5,6)
READ CYCLE3
(1,4)
ADDRESS
t
RC
t
OE
AA
t
CE2
OE
t
OH
t
t
t
t
(5,6)
CLZ
ACS2(6)
CE
OLZ
ACS1
t
t
OHZ
CHZ
(5)
(1,5,6)
LB,UB
t
BE
t
t
BA
BDO
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
and CE2 = V
IH.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .
R0201-BS616UV2019
5
Revision 1.1
Jan.
2004
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