1Mx8/512Kx16/256Kx32, 12 - 35ns, ZIP/SIMM/ASIMM
30A056-00
K
8 Megabit CMOS SRAM
DPS256X32L/DPS256X32W/DPS256X32WA
DESCRIPTION:
The DPS256X32L/DPS256X32W/DPS256X32WA is a
256K x 32 high density, high-speed Static Random Access
Memory (SRAM) module, intended for high performance
computers and digital signal processing applications. The
DPS256X32L/DPS256X32W/DPS256X32WA is comprised of
eight 256K x 4 devices surface mounted on an epoxy laminate
substrate.
FEATURES:
•
256K X 32, 512K x 16 or 1M x 8 Configuration
•
High Speed: 12*, 15, 17, 20, 25, 35ns
•
All Inputs and Outputs TTL Compatible
•
Fully Static Operation;
No Clock or Refresh Required
•
Equal Read Access and Write Cycle Time
•
Packages:
64-Pin ZIP
64-Pin SIMM
64-Pin Angled SIMM
*
Contact factory for availability.
PIN NAMES
A0 - A17
I/O0 - I/O31
CE0 - CE3
DID0 / DID1
OE
WE
V
DD
V
SS
Address Inputs
Data In/Out
Chip Enables
Density I.D. Pins
Output Enable
Write Enable
Power (+5V)
Ground
FUNCTIONAL BLOCK DIAGRAM
30A056-00
REV.
K
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS256X32L/DPS256X32W/DPS256X32WA
PIN-OUT DIAGRAM
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Dense-Pac Microsystems, Inc.
TRUTH TABLE
CEn
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
I/O Pin
HIGH-Z
HIGH-Z
D
OUT
D
IN
Supply
Current
Standby
Active
Active
Active
X = Don’t Care
RECOMMENDED OPERATING RANGE
2
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
3
0.8
V
T
A
Operating Temp.
0 +25
+70
°C
ABSOLUTE MAXIMUM RATINGS
4
Symbol
Parameter
Max.
Unit
T
STC
Storage Temperature
-40 to +125
°C
T
BIAS
Temperature Under Bias
-10 to + 85
°C
2
V
DD
Supply Voltage
-0.5 to + 7.0
V
V
ID
Input/Output Voltage
2
-0.5 to V
DD
+0.5 V
DID0 = VSS
DID1 = V
SS
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions Min. Max. Unit
V
IH
HIGH Voltage I
OH
= -4.0mA 2.4
-
V
V
IL
LOW Voltage
I
OL
= 8.0mA
0.4 V
CAPACITANCE
5
:
T
A
= 25
°
C, F = 1.0MHz
Symbol
Parameter
Max. Unit Condition
C
ADR
Address Input
50
C
CE
Chip Enable
25
pF
V
IN
= 0V
C
WE
Write Enable
60
C
OE
Output Enable
60
C
I/O
Data Input/Output
20
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
V
OL
V
OH
Characteristics
Input Leakage Current
Output Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
, CEn = V
IH
CEn = V
IL
, f = max., I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or V
IN
≤
V
SS
+0.2V,
CEn
≥
V
DD
-0.2, f = 0mHz
CEn = V
IH
, f = max.
I
OUT
= 8.0mA
I
OUT
= -4.0mA
15ns-35ns
12ns*
COMMERCIAL
Min.
Max.
Unit
µA
µA
mA
mA
mA
V
V
-40
-10
+40
+10
1440
1760
80
480
0.4
2.4
*
Contact factory for availability.
2
30A056-00
REV.
K
Dense-Pac Microsystems, Inc.
DPS256X32L/DPS256X32W/DPS256X32WA
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
5ns *
Input and Output
1.5V
Timing Reference Levels
* Transition measured between 0.8V and 2.2V.
Figure 1.
Output Load
** Including Probe and Jig Capacitance.
+5V
1480Ω
Output Load
Parameters Measured
except t
CLZ
, t
CHZ
, t
WHZ
, t
OW
, t
OLZ
and t
OHZ
t
CLZ
, t
CHZ
, t
WHZ
, t
OW
D
OUT
C
L
**
225Ω
Load
1
2
C
L
30pF
5pF
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
12ns†
15ns
17ns
20ns
25ns
35ns
No. Symbol
Parameter
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in LOW-Z
5, 7
Output Enable to Output Valid
Output Enable to Output in LOW-Z
5, 7
Chip Enable to Output in HIGH-Z
5, 7
Output Enable to Output in HIGH-Z
5, 7
Output Hold from Address Change
12
12
12
3
6
0
0
0
3
6
6
0
0
0
3
3
7
7
7
0
0
0
5
15
15
15
5
8
8
7
0
0
0
5
17
17
17
5
10
12
10
0
0
0
5
20
20
20
5
13
15
10
0
0
0
5
25
25
25
5
35
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
15
15
20
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE:
Over operating ranges
8
12ns†
15ns
17ns
20ns
25ns
35ns
No. Symbol
Parameter
10
12
11
13
14
15
16
17
18
19
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time ‡
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
5, 7
Data to Write Time Overlap
Data Hold Time from Write Time
Output Active from End of Write
5, 7
12
10
10
0
10
0
0
6
0
0
15
12
12
0
11
0
0
7
0
0
17
14
14
0
14
2
0
9
0
5
20
17
17
0
16
3
0
12
0
5
25
20
20
0
20
3
0
15
0
5
35
30
30
0
30
3
0
20
0
5
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
7
8
10
15
† Contact factory for availability.
‡ Valid for both Read and Write Cycles.
30A056-00
REV.
K
3
DPS256X32L/DPS256X32W/DPS256X32WA
Dense-Pac Microsystems, Inc.
READ CYCLE 2:
Address Controlled. WE is HIGH. CE and OE are LOW.
ADDRESS
DATA I/O
READ CYCLE 1:
CE Controlled. WE is HIGH.
ADDRESS
OE
CE
DATA I/O
WRITE CYCLE 1:
WE Controlled.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A056-00
REV.
K
4
Dense-Pac Microsystems, Inc.
DPS256X32L/DPS256X32W/DPS256X32WA
WRITE CYCLE 2:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1.
The DID0 and DID1 pins are used to identify memory
density when other density versions of the JEDEC STD
module can be installed in the same socket.
2. All voltages are with respect to V
SS
.
3. -2.0V min. for pulse width less than 20ns (V
IL
min.= -0.5V
at DC level).
4. Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
5. This parameter is guaranteed and not 100% tested.
6. Transition is measured at the point of
±
500mV from steady
state voltage.
7. When OE and CE are LOW and WE is HIGH, I/O pins are
in the output state,and input signals of opposite phase to
the outputs must not be applied.
8. The outputs are in a high impedance state when WE is
LOW.
ORDERING INFORMATION
30A056-00
REV.
K
5
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