PC755/745
PowerPC 755/745 RISC Microprocessor
Datasheet DS0828
FEATURES
•
18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)
•
15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)
•
733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz
(PC745)
•
Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
•
P
D
Typical 5.4W at 400 MHz, Full Operating Conditions
•
Nap, Doze and Sleep Modes for Power Savings
•
Superscalar (3 Instructions per Clock Cycle) Two Instruction +
Branch
•
4 Beta Byte Virtual Memory, 4‐GByte of Physical Memory
•
64‐bit Data and 32‐bit Address Bus Interface
•
32‐KB Instruction and Data Cache
•
Six Independent Execution Units
•
Write‐back and Write‐through Operations
•
f
INT
max = 400 MHz
•
f
BUS
max = 100 MHz
•
Voltage I/O 2.5V/3.3V; Voltage Int 2.0V
This document describes pertinent physical characteristics
of the PC755. For information on specific PC755 part
numbers covered by this or other specifications, see Section
”Table 11‐1 provides the e2v part numbering nomenclature
for the PC755 and PC745 devices fully addressed by this
document.” on page 59. For functional characteristics of the
processor, refer to the MPC750 RISC Microprocessor Family
User’s Manual.
To locate any published errata or updates for this docu‐
ment, refer to the website listed on the back cover of this
document.
Screening
This product is manufactured in full compliance with:
•
HiTCE CBGA According to e2v Standards
•
CBGA + CI‐CGA + FC‐PBGA up Screenings Based upon e2v
Standards
•
Full Military Temperature Ranges (T
C
= ‐55°C, T
J
= +125°C)
•
Industrial Temperature Ranges (T
C
= ‐40°C, T
J
= +110°C)
•
Commercial Temperature ranges (T
C
= 0°C, T
J
= +105°C)
Description
This document is primarily concerned with the PC755; however,
unless otherwise noted, all information here also applies to the
PC745. The PC755 and PC745 are reduced instruction set com‐
puting (RISC) microprocessors that implement the PowerPC
™
instruction set architecture.
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any
use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its
standard conditions of sale in respect of infringement of third party patents arising from the use of devices in accordance with information contained
herein.
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc
Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
Contact e2v by e‐mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.
© e2v technologies (uk) limited 2016
0828M–HIREL–02/16
PC755/745
1.
OVERVIEW
The PC755 is targeted for low‐cost, low‐power systems and supports the following power management
features: doze, nap, sleep, and dynamic power management. The PC755 consists of a processor core
and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The PC745 is
identical to the PC755 except it does not support the L2 cache interface.
Figure 1‐1 shows a block diagram of the PC755.
Figure 1‐1.
PC755 Block Diagram
128-Bit
(4 Instructions)
Instruction Unit
Fetcher
Branch Processing
Unit
BTIC
64-Entry
BHT
CTR
LR
Additional Features
* Time Base Counter/Decrementer
* Clock Multiplier
* JTAG/COP Interface
* Thermal/Power Management
* Performance Monitor
Instruction Queue
(6-Word)
Instruction MMU
SRs
(Shadow)
ITLB
IBAT
Array
Tags
32-Kbyte
I Cache
2 Instructions
Dispatch Unit
64-Bit
(2 Instructions)
Reservation Station Reservation Station Reservation Station
GPR File
Rename Buffers
(6)
Reservation Station
(2-Entry)
FPR File
Rename Buffers
(6)
Reservation Station
Integer Unit 1
Integer Unit 2
System Register
Unit
32-Bit
Load/Store Unit
64-Bit
+
(EA Calculation)
Store Queue
64-Bit
Floating-Point
Unit
+ x :
32-Bit
+
+ x :
FPSCR
FPSCR
CR
32-Bit
PA
Completion Unit
Reorder Buffer
(6-Entry)
Data MMU
SRs
(Original)
DTLB
EA
60x Bus Interface Unit
64-Bit
Instruction Fetch Queue
L1 Castout Queue
L2 Bus Interface
Unit
L2 Castout Queue
DBAT
Array
Tags
32-Kbyte
D Cache
Data Load Queue
L2 Controller
L2CR
32-Bit Address Bus
32-/64-Bit Data Bus
17-Bit L2 Address Bus
64-Bit L2 Data Bus
L2 Tags
Not in the PC745
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© e2v technologies (uk) limited 2016
PC755/745
2.
FEATURES
This section summarizes features of the PC755 implementation of the PowerPC architecture. Major
features of the PC755 are as follows:
• Branch processing unit
– Four instructions fetched per clock
– One branch processed per cycle (plus resolving two speculations)
– Up to one speculative stream in execution, one additional speculative stream in fetch
– 512‐entry branch history table (BHT) for dynamic prediction
– 64‐entry, four‐way set‐associative branch target instruction cache (BTIC) for eliminating
branch delay slots
• Dispatch unit
– Full hardware detection of dependencies (resolved in the execution units)
– Dispatch two instructions to six independent units (system, branch, load/store, fixed‐point
unit 1, fixed‐point unit 2, floating‐point)
– Serialization control (predispatch, postdispatch, execution serialization)
• Decode
– Register file access
– Forwarding control
– Partial instruction decode
• Completion
– Six‐entry completion buffer
– Instruction tracking and peak completion of two instructions per cycle
– Completion of instructions in program order while supporting out‐of‐order instruction
execution, completion serialization, and all instruction flow changes
• Fixed point units (FXUs) that share 32 GPRs for integer operands
– Fixed Point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical
– Fixed Point Unit 2 (FXU2): shift, rotate, arithmetic, logical
– Single‐cycle arithmetic, shifts, rotates, logical
– Multiply and divide support (multi‐cycle)
– Early out multiply
• Floating‐point unit and a 32‐entry FPR file
– Support for IEEE standard 754 single‐ and double‐precision floating‐point arithmetic
– Hardware support for divide
– Hardware support for denormalized numbers
– Single‐entry reservation station
– Supports non‐IEEE mode for time‐critical operations
– Three‐cycle latency, one‐cycle throughput, single‐precision multiply‐add
– Three‐cycle latency, one‐cycle throughput, double‐precision add
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PC755/745
– Four‐cycle latency, two‐cycle throughput, double‐precision multiply‐add
• System unit
– Executes CR logical instructions and miscellaneous system instructions
– Special register transfer instructions
• Load/store unit
– One‐cycle load or store cache access (byte, half‐word, word, double word)
– Effective address generation
– Hits under misses (one outstanding miss)
– Single‐cycle unaligned access within double‐word boundary
– Alignment, zero padding, sign extend for integer register file
– Floating‐point internal format conversion (alignment, normalization)
– Sequencing for load/store multiples and string operations
– Store gathering
– Cache and TLB instructions
– Big‐ and little‐endian byte addressing supported
• Level 1 cache structure
– 32K, 32‐byte line, eight‐way set‐associative instruction cache (iL1)
– 32K, 32‐byte line, eight‐way set‐associative data cache (dL1)
– Cache locking for both instruction and data caches, selectable by group of ways
– Single‐cycle cache access
– Pseudo least‐recently‐used (PLRU) replacement
– Copy‐back or write‐through data cache (on a page per page basis)
– MEI data cache coherency maintained in hardware
– Nonblocking instruction and data cache (one outstanding miss under hits)
– No snooping of instruction cache
• Level 2 (L2) cache interface (not implemented on PC745)
– Internal L2 cache controller and tags; external data SRAMs
– 256K, 512K, and 1 Mbyte two‐way set‐associative L2 cache support
– Copy‐back or write‐through data cache (on a page basis, or for all L2)
– Instruction‐only mode and data‐only mode
– 64‐byte (256K/512K) or 128‐byte (1M) sectored line size
– Supports flow through (register‐buffer) synchronous BurstRAMs, pipelined (register‐
register) synchronous BurstRAMs (3‐1‐1‐1 or strobeless 4‐1‐1‐1) and pipelined (register‐
register) late write synchronous BurstRAMs
– L2 configurable to cache, private memory, or split cache/private memory
– Core‐to‐L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
– 64‐bit data bus
– Selectable interface voltages of 2.5 and 3.3 V
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PC755/745
– Parity checking on both L2 address and data
• Memory management unit
– 128‐entry, two‐way set‐associative instruction TLB
– 128‐entry, two‐way set‐associative data TLB
– Hardware reload for TLBs
– Hardware or optional software tablewalk support
– Eight instruction BATs and eight data BATs
– Eight SPRGs, for assistance with software tablewalks
– Virtual memory support for up to 4 exabytes (252) of virtual memory
– Real memory support for up to 4 gigabytes (232) of physical memory
• Bus interface
– Compatible with 60x processor interface
– 32‐bit address bus
– 64‐bit data bus, 32‐bit mode selectable
– Bus‐to‐core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x
supported
– Selectable interface voltages of 2.5 and 3.3 V
– Parity checking on both address and data buses
• Power management
– Low‐power design with thermal requirements very similar to PC740/PC750
– Three static power saving modes: doze, nap, and sleep
– Dynamic power management
• Integrated thermal management assist unit
– On‐chip thermal sensor and control logic
– Thermal management interrupt for software regulation of junction temperature
• Testability
– LSSD scan design
– IEEE 1149.1 JTAG interface
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© e2v technologies (uk) limited 2016
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