PC8349/E
PowerQUICC II Pro Integrated Host
Processor Hardware Specifications
Datasheet -
Preliminary Specification
Features
•
Embedded PowerPC e300 Processor Core; Operates at up to 667 MHz
– Pd Maximum : 5W @ 667 MHz (V
DD
= 1.3V), 3.6W @ 533 MHz (V
DD
= 1.2V)
– 32-Kbyte Instruction Cache, 32-Kbyte Data Cache
– Dynamic Power Management
Double Data Rate, DDR1/DDR2 SDRAM Memory Controller
– 32- or 64-bit Data Interface, up to 400 MHz Data Rate
Dual Three-speed (10/100/1000) Ethernet Controllers (TSECs)
Dual PCI Interfaces
Universal Serial Bus (USB) Dual Role and Multi-port Host Controller
Local Bus Controller (LBC)
Programmable Interrupt Controller (PIC)
Dual Industry-standard I
2
C Interfaces
DMA Controller
DUART
Serial Peripheral Interface (SPI) for Master or Slave
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•
•
•
•
•
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•
Overview
The PC8349/E PowerQUICC
™
II Pro is a next generation PowerQUICC II integrated host processor. The PC8349/E con-
tains a PowerPC™ processor core built on Power Architecture
™
technology with system logic for networking, storage, and
general-purpose embedded applications. For functional characteristics of the processor refer to the
PC8349/E Power-
QUICC
™
II Pro Integrated Host Processor Family Reference Manual.
To locate published errata or updates for this document, refer to the PC8349/E product summary page on our website
listed on the back cover of this document or, contact your local Freescale sales office.
Note:
The information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending
in A or B).
See
Section 22.1 ”Part Numbers Fully Addressed by This Document” on page 73,
for silicon revision level determination.
Screening
•
Full Military Temperature Range (T
C
= –55° C, T
J
= +125°C)
•
Industrial Temperature Range (T
C
= –40°C, T
J
= +110°C)
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2010
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1. Overview
This section provides a high-level overview of the PC8349/E features.
Figure 1-1
shows the major func-
tional units within the PC8349/E.
Figure 1-1.
DDR/DD
R2
ROM
SDRAM
IRQs
PC8349/E Block Diagram
DDR/DDR2
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
Security Engine
Serial Peripheral
Interface
DUART
Arbiter Bus
Monitor
e300 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Coherent System Bus
64/32b PCI Controller
Sequencer
SEQ
0/32b PCI Controller
DMA Controller
SPI
Serial
PCI1
PCI2
DMA
I
2
C
USB0
USB1
GPIO
I C Interfaces
2
TSEC
USB Hi - Speed
Host Device
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
MII, GMII, TBI,
RTBI, RGMII
TSEC
General Purpose I/O
10/100/1Gb
Major features of the PC8349/E are as follows:
• Embedded PowerPC e300 processor core; operates at up to 667 MHz
– High-performance, superscalar processor core
– Floating-point, integer, load/store, system register, and branch processing units
– 32-Kbyte instruction cache, 32-Kbyte data cache
– Lockable portion of L1 cache
– Dynamic power management
– Software-compatible with the other Freescale processor families that implement Power
Architecture technology
• Double data rate, DDR1/DDR2 SDRAM memory controller
– Programmable timing supporting DDR1 and DDR2 SDRAM
– 32- or 64-bit data interface, up to 400 MHz data rate
– Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
– DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
– Full error checking and correction (ECC) support
– Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
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– Contiguous or discontiguous memory mapping
– Read-modify-write support
– Sleep-mode support for SDRAM self refresh
– Auto refresh
– On-the-fly power management using CKE
– Registered DIMM support
– 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
– Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®
802.3ac® standards
– Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
– Buffer descriptors are backward-compatible with PC8260 and PC860T 10/100 programming
models
– 9.6-Kbyte jumbo frame support
– RMON statistics support
– Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
– MII management interface for control and status
– Programmable CRC generation and checking
• Dual PCI interfaces
– Designed to comply with
PCI Specification Revision 2.3
– Data bus width options:
– Dual 32-bit data PCI interfaces operating at up to 66 MHz
– Single 64-bit data PCI interface operating at up to 66 MHz
– PCI 3.3-V compatible
– PCI host bridge capabilities on both interfaces
– PCI agent mode on PCI1 interface
– PCI-to-memory and memory-to-PCI streaming
– Memory prefetching of PCI read accesses and support for delayed read transactions
– Posting of processor-to-PCI and PCI-to-memory writes
– On-chip arbitration supporting five masters on PCI1, three masters on PCI2
– Accesses to all PCI address spaces
– Parity supported
– Selectable hardware-enforced coherency
– Address translation units for address mapping between host and peripheral
– Dual address cycle for target
– Internal configuration registers accessible from PCI
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs):
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– Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
– Data encryption standard (DES) execution unit (DEU)
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
– Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
– XOR parity generation accelerator for RAID applications
– ARC four execution unit (AFEU)
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Random number generator (RNG)
– Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
• Universal serial bus (USB) dual role controller
– USB on-the-go mode with both device and host functionality
– Complies with USB specification Rev. 2.0
– Can operate as a stand-alone USB device
– One upstream facing port
– Six programmable USB endpoints
– Can operate as a stand-alone USB host controller
– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
– External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
• Universal serial bus (USB) multi-port host controller
– Can operate as a stand-alone USB host controller
– USB root hub with one or two downstream-facing ports
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– Enhanced host controller interface (EHCI) compatible
– Complies with
USB Specification Rev. 2.0
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
– Direct connection to a high-speed device without an external hub
– External PHY with serial and low-pin count (ULPI) interfaces
• Local bus controller (LBC)
– Multiplexed 32-bit address and data operating at up to 133 MHz
– Eight chip selects for eight external slaves
– Up to eight-beat burst transfers
– 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
– Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
– Parity support
– Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
– Functional and programming compatibility with the PC8260 interrupt controller
– Support for 8 external and 35 internal discrete interrupt sources
– Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
– Programmable highest priority request
– Four groups of interrupts with programmable priority
– External and internal interrupts directed to host processor
– Redirects interrupts to external INTA pin in core disable mode.
– Unique vector number for each interrupt source
• Dual industry-standard I
2
C interfaces
– Two-wire interface
– Multiple master support
– Master or slave I
2
C mode support
– On-chip digital filtering rejects spikes on the bus
– System initialization data optionally loaded from I
2
C-1 EPROM by boot sequencer
embedded hardware
• DMA controller
– Four independent virtual channels
– Concurrent execution across multiple channels with programmable bandwidth control
– Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3],
DMA_DDONE[0:3]
– All channels accessible to local core and remote PCI masters
– Misaligned transfer capability
– Data chaining and direct mode
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PCB Design
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