PC8572VZFATLD datasheet, PDF - EEWORLD Datasheet

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PC8572VZFATLD: DescriptionRISC Microprocessor, 32-Bit, 1200MHz, CMOS, PBGA1023; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，126 Pages; Manufacturere2v technologies

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PC8572VZFATLD Overview

RISC Microprocessor, 32-Bit, 1200MHz, CMOS, PBGA1023

PC8572VZFATLD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	e2v technologies
Parts packaging code	BGA
package instruction	FCBGA-1023
Contacts	1023
Reach Compliance Code	compli
Address bus width	16
bit size	32
boundary scan	YES
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B1023
length	33 mm
low power mode	YES
Number of terminals	1023
Maximum operating temperature	110 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1023,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.1,1.8/3.3 V
Certification status	Not Qualified
Maximum seat height	3.38 mm
speed	1200 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	33 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PC8572/E

PowerQUICC III Integrated

Processor Hardware

Datasheet -

Preliminary Specification

Features

•

Dual Embedded e500 Cores, Scaling up to 1.5 GHz

•

– 6897 MIPS at 1500 MHz (Estimated Dhrystone 2.1)

36-bit Physical Addressing

Enhanced Hardware and Software Debug Support

Double-precision Floating Point Unit

Memory Management Unit

Integrated L1/L2 Cache

– L1 Cache: 32 KB Data and 32 KB Instruction Cache with Line-locking

Support

– Shared L2 Cache: 1 MB with ECC

– L1 and L2 Hardware Coherency

– L2 Configurable as SRAM, Cache and I/O Transactions can be Stashed Into L2 Cache Regions

Integrated DDR Memory Controller with Full ECC Support, Supporting:

– 333 MHz Clock Rate (667 MHz data rate), 64-bit, 1.8V SSTL, DDR2 SDRAM

– 400 MHz Clock Rate (up to 800 MHz Data Rate), 64-bit, 1.5V SSTL, DDR3 SDRAM

Application Acceleration Platform

– Advanced TLU

– Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption

Algorithms

– Integrated PME (Regular Expression)

– Packet Deflate Engine

– Integrated Security Engine with XOR

Four On-chip, Triple-speed Ethernet Controllers Supporting 10 and 100 Mbps, and 1 Gbps Ethernet/IEEE 802.3 Networks with

MII, RMII, GMII, SGMII, RGMII, RTBI and TBI Physical Interfaces and IEEE 1588

– TCP/IP Checksum Acceleration and Advanced QoS Features

– Lossless Flow Control

General-purpose I/O

Serial RapidIO and PCI Express High-speed Interconnect Interfaces

On-chip Network (OCeaN) Switch Fabric

133 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller

Dual Integrated DMA Controller

Dual I

C and DUARTS

Programmable interrupt Controller

•

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2010

0934C–HIREL–09/10

PC8572/E [Preliminary]

1.1

Key Features

The following list provides an overview of the PC8572E feature set:

• Two high-performance 32-bit Book E-enhanced cores that implement the Power Architecture

™

technology:

– Each core is identical to the core within the PC8548 processor

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches

can be locked entirely or on a per-line basis, with separate locking for instructions and data

– Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operations. These instructions use

both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU

– Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions

– Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs

– 36-bit real addressing

– Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte-4-Gbyte page sizes

– Enhanced hardware and software debug support

– Performance monitor facility that is similar to, but separate from, the PC8572E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some fea-

tures that this device implements more specifically. An understanding of these differences can be critical

to ensure proper operation.

• 1 Mbyte L2 cache/SRAM

– Shared by both cores

– Flexible configuration and individually configurable per core

– Full ECC support on 64-bit boundary in both cache and SRAM modes

– Cache mode supports instruction caching, data caching, or both

– External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing)

– 1, 2, or 4 ways can be configured for stashing only

– Eight-way set-associative cache organization (32-byte cache lines)

– Supports locking entire cache or selected lines. Individual line locks are set and cleared

through Book E instructions or by externally mastered transactions

– Global locking and flash clearing done through writes to L2 configuration registers

– Instruction and data locks can be flash cleared separately

– Per-way allocation of cache region to a given processor

– SRAM features include the following:

– 1, 2, 4, or 8 ways can be configured as SRAM

– I/O devices access SRAM regions by marking transactions as snoopable (global)

– Regions can reside at any aligned location in the memory map

0934C–HIREL–09/10

e2v semiconductors SAS 2010

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