PC8572E
PowerQUICC III Integrated Processor
Hardware Specifications
Datasheet DS0934
FEATURES
•
Dual Embedded e500 Cores, Scaling up to 1.5 GHz
– 6897 MIPS at 1500 MHz (Estimated Dhrystone 2.1)
•
36-bit Physical Addressing
•
Enhanced Hardware and Software Debug Support
•
Double-precision Floating Point Unit
•
Memory Management Unit
•
Integrated L1/L2 Cache
– L1 Cache: 32 KB Data and 32 KB Instruction Cache with
Line-locking Support
– Shared L2 Cache: 1 MB with ECC
– L1 and L2 Hardware Coherency
– L2 Configurable as SRAM, Cache and I/O Transactions can
be Stashed Into L2 Cache Regions
•
Integrated DDR Memory Controller with Full ECC Support,
Supporting:
– 333 MHz Clock Rate (667 MHz data rate), 64-bit, 1.8V
SSTL, DDR2 SDRAM
– 400 MHz Clock Rate (up to 800 MHz Data Rate), 64-bit,
1.5V SSTL, DDR3 SDRAM
•
Application Acceleration Platform
– Advanced TLU
– Integrated Security Engine Supporting DES, 3DES, MD-5,
SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4
Encryption Algorithms
– Integrated PME (Regular Expression)
– Packet Deflate Engine
– Integrated Security Engine with XOR
•
Four On-chip, Triple-speed Ethernet Controllers Supporting
10 and 100 Mbps, and 1 Gbps Ethernet/IEEE 802.3 Networks
with MII, RMII, GMII, SGMII, RGMII, RTBI and TBI Physical
Interfaces and IEEE 1588
– TCP/IP Checksum Acceleration and Advanced QoS
Features
– Lossless Flow Control
•
General-purpose I/O
•
Serial RapidIO and PCI Express High-speed Interconnect
Interfaces
•
On-chip Network (OCeaN) Switch Fabric
•
133 MHz, 32-bit, 3.3V I/O, Local Bus with Memory
Controller
•
Dual Integrated DMA Controller
•
Dual I
2
C and DUARTS
•
Programmable interrupt Controller
•
IEEE 1149.1 JTAG Test Access Port
•
1.1V Core Voltage with 3.3V/2.5V/1.8V I/O
•
1023-pin PBGA Package
OVERVIEW
This section provides a high-level overview of the fea-
tures of the PC8572E processor.
Figure 1-1
shows the
major functional units within the PC8572E.
This is a preliminary document, and contains informa-
tion which is subject to change.
SCREENING
•
Full Military Temperature Range (T
C
= –55°C, T
J
= +125°C)
(to be confirmed)
•
Industrial Temperature Range (T
C
= –40°C, T
J
= +110°C)
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any
use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its
standard conditions of sale in respect of infringement of third party patents arising from the use of devices in accordance with information contained
herein.
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc
Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
Contact e2v by e-mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.
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PC8572E
1.
BLOCK DIAGRAM
PC8572E Block Diagram
64b DDR2/DDR3
Memory Controller
64b DDR2/DDR3
Memory Controller
Security
Engine
Enhanced Local Bus
Controller
XOR
Engine
Table Lookup
Unit
Table Lookup
Unit
Programmable Interrupt
Controller (PIC)
DUART
I C
Controller
I C
Controller
eTSEC
10/1 00/1 Gb
eTSEC
10/1 00/1 Gb
eTSE C
10/ 100/ 1G b
eTSE C
10/ 100/ 1G b
FEC
4-Channel DMA
Controller
External control
4-Channel DMA
Controller
External control
Serial RapidIO
Messaging Unit
2
2
Figure 1-1.
DDR2/3
SDRAM
DDR2/3
SDRAM
Pattern Matching
Engine
Deflate
Engine
PC8572E
e500 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
(NOR/NAND)
Flash
GPIO
e500
Coherency
Module
Core
Complex
Bus
1-Mbyte L2
Cache/
SRAM
e500 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
IRQs
Serial
I C
I C
MII, GMII, TBI,
RTBI, RGMII,
RMII, SGMII, FIFO
MII, GMII, TBI,
RTBI, RGMII,
RMII, SGMII, FIFO
MII, GMII, TBI,
RTBI, RGMII,
RMII, SGMII, FIFO
RTBI, RGMII,
RMII, SGMII
2
2
OceaN
Switch
Fabric
Serial RapidIO
PCI Express
4x Serial RapidIO
x8/x4/x2/x1 PCI Expres
MII
2
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© e2v technologies (uk) limited 2016
PC8572E
1.1
Key Features
The following list provides an overview of the PC8572E feature set:
• Two high-performance 32-bit Book E-enhanced cores that implement the Power Architecture
™
technology:
– Each core is identical to the core within the PC8548 processor
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches
can be locked entirely or on a per-line basis, with separate locking for instructions and data
– Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use
both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU
– Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions
– Double-precision floating-point APU. Provides an instruction set for double-precision (64-
bit) floating-point instructions that use the 64-bit GPRs
– 36-bit real addressing
– Memory management unit (MMU). Especially designed for embedded applications.
Supports 4-Kbyte-4-Gbyte page sizes
– Enhanced hardware and software debug support
– Performance monitor facility that is similar to, but separate from, the PC8572E performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some fea-
tures that this device implements more specifically. An understanding of these differences can be
critical to ensure proper operation.
• 1 Mbyte L2 cache/SRAM
– Shared by both cores
– Flexible configuration and individually configurable per core
– Full ECC support on 64-bit boundary in both cache and SRAM modes
– Cache mode supports instruction caching, data caching, or both
– External masters can force data to be allocated into the cache through programmed
memory ranges or special transaction types (stashing)
– 1, 2, or 4 ways can be configured for stashing only
– Eight-way set-associative cache organization (32-byte cache lines)
– Supports locking entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions
– Global locking and flash clearing done through writes to L2 configuration registers
– Instruction and data locks can be flash cleared separately
– Per-way allocation of cache region to a given processor
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PC8572E
– SRAM features include the following:
– 1, 2, 4, or 8 ways can be configured as SRAM
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses
• e500 coherency module (ECM) manages core and intra-system transactions
• Address translation and mapping unit (ATMU)
– Twelve local access windows define mapping within local 36-bit address space
– Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI Express
– Four inbound windows plus a default window on serial RapidIO
™
– Four outbound windows plus default translation for PCI Express
– Eight outbound windows plus default translation for serial RapidIO with segmentation
and sub-segmentation support
• Two 64-bit DDR2/DDR3 memory controllers
– Programmable timing supporting DDR2 and DDR3 SDRAM
– 64-bit data interface per controller
– Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per
controller
– DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
– Full ECC support
– Page mode support
– Up to 32 simultaneous open pages for DDR2 or DDR3
– Contiguous or discontiguous memory mapping
– Cache line, page, bank, and super-bank interleaving between memory controllers
– Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
– Sleep mode support for self-refresh SDRAM
– On-die termination support when using DDR2 or DDR3
– Supports auto refreshing
– On-the-fly power management using CKE signal
– Registered DIMM support
– Fast memory access via JTAG port
– 1.8-V SSTL_1.8 compatible I/O
– Support 1.5-V operation for DDR3. The detail is TBD pending on official release of
appropriate industry specifications
– Support for battery-backed main memory
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PC8572E
• Programmable interrupt controller (PIC)
– Programming model is compliant with the OpenPIC architecture
– Supports 16 programmable interrupt and processor task priority levels
– Supports 12 discrete external interrupts
– Supports 4 message interrupts per processor with 32-bit messages
– Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
– Four global high resolution timers/counters per processor that can generate interrupts
– Supports a variety of other internal interrupt sources
– Supports fully nested interrupt delivery
– Interrupts can be routed to external pin for external processing
– Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
– Interrupt summary registers allow fast identification of interrupt source
• Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE,
SSL/TLS, SRTP, 802.16e, and 3GPP
– Four crypto-channels, each supporting multi-command descriptor chains
– Dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
– PKEU: Public Key Execution Unit
– RSA and Diffie-Hellman; programmable field size up to 4096 bits
– Elliptic curve cryptography with F
2
m and F(p) modes and programmable field size up to
1023 bits
– DEU: Data Encryption Standard execution unit
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB, CBC and OFB-64 modes for both DES and 3DES
– AESU: Advanced Encryption Standard Unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, CCM, GCM, CMAC, OFB-128, CFB-128, and LRW modes
– 128-, 192-, and 256-bit key lengths
– AFEU: ARC Four Execution Unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– MDEU: Message Digest Execution Unit
– SHA-1 with 160-bit message digest
– SHA-2 (SHA-256, SHA-384, SHA-512)
– MD5 with 128-bit message digest
– HMAC with all algorithms
5
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