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74LVC1G11GV

Description
8-Bit Addressable Latches 16-SOIC -40 to 85
Categorylogic    logic   
File Size57KB,14 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Environmental Compliance
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74LVC1G11GV Overview

8-Bit Addressable Latches 16-SOIC -40 to 85

74LVC1G11GV Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instructionTSOP, TSOP6,.11,37
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G6
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
MaximumI(ol)0.024 A
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
method of packingTAPE AND REEL
power supply3.3 V
Prop。Delay @ Nom-Su6.2 ns
Certification statusNot Qualified
Schmitt triggerNO
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
74LVC1G11
Single 3-input AND gate
Rev. 01 — 30 November 2004
Product data sheet
1. General description
The 74LVC1G11 is a high-performance, low-voltage, Si-gate CMOS device and superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
The 74LVC1G11 provides a single 3-input AND gate.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8-B/JESD36 (2.7 V to 3.6 V).
±24
mA output drive (V
CC
= 3.0 V)
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
s
s
s
s
s
s
s

74LVC1G11GV Related Products

74LVC1G11GV 74LVC1G11 74LVC1G11GW
Description 8-Bit Addressable Latches 16-SOIC -40 to 85 8-Bit Addressable Latches 16-SOIC -40 to 85 8-Bit Addressable Latches 16-SOIC -40 to 85
Is it Rohs certified? conform to - conform to
Maker Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.)
package instruction TSOP, TSOP6,.11,37 - TSSOP, TSSOP6,.08
Reach Compliance Code unknow - unknow
JESD-30 code R-PDSO-G6 - R-PDSO-G6
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type AND GATE - AND GATE
MaximumI(ol) 0.024 A - 0.024 A
Number of terminals 6 - 6
Maximum operating temperature 125 °C - 125 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code TSOP - TSSOP
Encapsulate equivalent code TSOP6,.11,37 - TSSOP6,.08
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL - TAPE AND REEL
power supply 3.3 V - 3.3 V
Prop。Delay @ Nom-Su 6.2 ns - 6.2 ns
Certification status Not Qualified - Not Qualified
Schmitt trigger NO - NO
Nominal supply voltage (Vsup) 3.3 V - 3.3 V
surface mount YES - YES
technology CMOS - CMOS
Temperature level AUTOMOTIVE - AUTOMOTIVE
Terminal form GULL WING - GULL WING
Terminal pitch 0.95 mm - 0.635 mm
Terminal location DUAL - DUAL

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