S1C17651B00E10L datasheet, PDF

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S1C17651B00E10L: Description16-BIT, FLASH, 2MHz, RISC MICROCONTROLLER, PBGA; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，216 Pages; ManufacturerSeiko Epson Corporation

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S1C17651B00E10L Overview

16-BIT, FLASH, 2MHz, RISC MICROCONTROLLER, PBGA

S1C17651B00E10L Parametric

Parameter Name	Attribute value
Maker	Seiko Epson Corporation
Parts packaging code	BGA
package instruction	BGA,
Reach Compliance Code	unknow
Has ADC	NO
Address bus width	16
bit size	16
maximum clock frequency	4.2 MHz
DAC channel	NO
DMA channel	NO
External data bus width	32
JESD-30 code	X-PBGA-B
Number of I/O lines	12
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	UNSPECIFIED
Package form	GRID ARRAY
ROM programmability	FLASH
speed	2 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	2 V
Nominal supply voltage	2.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal location	BOTTOM
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

S1C17651

Technical Manual

Rev.1.0

CONTENTS

– Contents –

1 Overview........................................................................................................................1-1

1.1 Features ...........................................................................................................................1-1

1.2 Block Diagram ..................................................................................................................1-2

1.3 Pins ..................................................................................................................................1-3

1.3.1 Pin Configuration Diagram .................................................................................1-3

1.3.2 Pin Descriptions .................................................................................................1-5

2 CPU ................................................................................................................................2-1

2.1

2.2

2.3

2.4

2.5

Features of the S1C17 Core ............................................................................................2-1

CPU Registers .................................................................................................................2-2

Instruction Set ..................................................................................................................2-2

Reading PSR ...................................................................................................................2-5

Processor Information ......................................................................................................2-6

3 Memory Map, Bus Control ...........................................................................................3-1

3.1 Bus Cycle .........................................................................................................................3-1

3.1.1 Restrictions on Access Size...............................................................................3-2

3.1.2 Restrictions on Instruction Execution Cycles .....................................................3-2

3.2 Flash Area ........................................................................................................................3-2

3.2.1 Embedded Flash Memory..................................................................................3-2

3.2.2 Flash Programming ...........................................................................................3-2

3.2.3 Protect Bits ........................................................................................................3-2

3.2.4 Flash Memory Read Wait Cycle Setting ...........................................................3-3

FLASHC Read Wait Control Register (FLASHC_WAIT) ........................................................... 3-3

3.3 Internal RAM Area............................................................................................................3-3

3.3.1 Embedded RAM ................................................................................................3-3

IRAM Size Register (MISC_IRAMSZ) ....................................................................................... 3-4

3.4 Display RAM area ............................................................................................................3-4

3.5 Internal Peripheral Area ...................................................................................................3-4

3.5.1 Internal Peripheral Area 1 (0x4000–) .................................................................3-4

3.5.2 Internal Peripheral Area 2 (0x5000–) .................................................................3-5

3.6 S1C17 Core I/O Area .......................................................................................................3-5

4 Power Supply ................................................................................................................4-1

4.1 Power Supply Voltage (V

) .............................................................................................4-1

4.2 Flash Programming Power Supply Voltage (V

) .............................................................4-1

4.3 Internal Power Supply Circuit ...........................................................................................4-1

4.3.1 V

and V

OSC

Regulators....................................................................................4-1

4.3.2 LCD Power Supply Circuit..................................................................................4-2

4.3.3 Heavy Load Protection Mode.............................................................................4-3

4.4 Control Register Details ...................................................................................................4-3

LCD Booster Clock Control Register (LCD_BCLK) ................................................................... 4-3

LCD Voltage Regulator Control Register (LCD_VREG) ............................................................ 4-4

Control Register (VD1_CTL) ............................................................................................... 4-5

5 Initial Reset ...................................................................................................................5-1

5.1 Initial Reset Sources ........................................................................................................5-1

5.1.1 #RESET Pin .......................................................................................................5-1

5.1.2 P0 Port Key-Entry Reset ...................................................................................5-1

5.1.3 Resetting by the Watchdog Timer ......................................................................5-1

5.2 Initial Reset Sequence .....................................................................................................5-2

5.3 Initial Settings After an Initial Reset ................................................................................5-2

S1C17651 TECHNICAL MANUAL

Seiko Epson Corporation

CONTENTS

6 Interrupt Controller (ITC) .............................................................................................6-1

6.1 ITC Module Overview .......................................................................................................6-1

6.2 Vector Table ......................................................................................................................6-2

Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) .............................. 6-3

6.3 Control of Maskable Interrupts .........................................................................................6-3

6.3.1 Interrupt Control Bits in Peripheral Modules ......................................................6-3

6.3.2 ITC Interrupt Request Processing .....................................................................6-3

6.3.3 Interrupt Processing by the S1C17 Core ...........................................................6-4

6.4 NMI...................................................................................................................................6-4

6.5 Software Interrupts ...........................................................................................................6-4

6.6 HALT and SLEEP Mode Cancellation ..............................................................................6-5

6.7 Control Register Details ...................................................................................................6-5

Interrupt Level Setup Register

(ITC_LVx) ............................................................................... 6-5

7 Clock Generator (CLG).................................................................................................7-1

7.1 CLG Module Overview .....................................................................................................7-1

7.2 CLG Input/Output Pins .....................................................................................................7-2

7.3 Oscillators ........................................................................................................................7-2

7.3.1 OSC3B Oscillator ...............................................................................................7-2

7.3.2 OSC3A Oscillator ...............................................................................................7-4

7.3.3 OSC1 Oscillator .................................................................................................7-4

7.4 System Clock Switching ...................................................................................................7-7

7.5 CPU Core Clock (CCLK) Control .....................................................................................7-8

7.6 Peripheral Module Clock (PCLK) Control .........................................................................7-8

7.7 Clock External Output (FOUTA, FOUTB) .........................................................................7-9

7.8 Control Register Details ..................................................................................................7-10

Clock Source Select Register (CLG_SRC) .............................................................................. 7-11

Oscillation Control Register (CLG_CTL) .................................................................................. 7-12

FOUTA Control Register (CLG_FOUTA) .................................................................................. 7-13

FOUTB Control Register (CLG_FOUTB) ................................................................................. 7-14

Oscillation Stabilization Wait Control Register (CLG_WAIT) .................................................... 7-15

PCLK Control Register (CLG_PCLK) ....................................................................................... 7-17

CCLK Control Register (CLG_CCLK)....................................................................................... 7-18

8 Theoretical Regulation (TR) .........................................................................................8-1

8.1 TR Module Overview ........................................................................................................8-1

8.2 TR Output Pin...................................................................................................................8-1

8.3 Theoretical Regulation Control .........................................................................................8-1

8.3.1 Setting Regulation Values ..................................................................................8-1

8.3.2 Executing Theoretical Regulation ......................................................................8-2

8.3.3 Regulated Clock External Monitor .....................................................................8-2

8.4 Control Register Details ...................................................................................................8-3

TR Control Register (TR_CTL) .................................................................................................. 8-3

TR Value Register (TR_VAL) ..................................................................................................... 8-3

9 Real-Time Clock (RTC) .................................................................................................9-1

9.1 RTC Module Overview .....................................................................................................9-1

9.2 RTC Counters ..................................................................................................................9-1

9.3 RTC Control .....................................................................................................................9-3

9.3.1 Operating Clock Control.....................................................................................9-3

9.3.2 12-hour/24-hour mode selection .......................................................................9-3

9.3.3 RTC Start/Stop ..................................................................................................9-3

9.3.4 Counter Settings ................................................................................................9-3

9.3.5 Counter Read ....................................................................................................9-4

Seiko Epson Corporation

S1C17651 TECHNICAL MANUAL

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