ZL50410GDG2 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> ZL50410GDG2

ZL50410GDG2: DescriptionLAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208; CategoryWireless rf/communication Telecom circuit; File Size2MB，146 Pages; ManufacturerCONEXANT; Websitehttp://www.conexant.com/

Download Datasheet Parametric Compare View All

ZL50410GDG2 Overview

LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208

ZL50410GDG2 Parametric

Parameter Name	Attribute value
Maker	CONEXANT
Parts packaging code	BGA
package instruction	LBGA,
Contacts	208
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	17 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm

Preview

Download Datasheet

View All

ZL50410

Managed 8FE + 1GE Layer-2

Ethernet Switch

Data Sheet

Zarlink Features

•

Integrated Single-Chip 10/100/1000 Mbps

Ethernet Switch

• Eight 10/100 Mbps auto-negotiating Fast

Ethernet (FE) ports with RMII, MII, GPSI,

Reverse MII & Reverse GPSI interface options

• One 10/100/1000 Mbps auto-negotiating port

with GMII & MII interface options, that can be

used as a WAN uplink or as a 9th port

• a 10/100 Mbps Fast Ethernet (FE) CPU port

with Reverse MII interface option

Embedded 2.0 Mbits (256 KBytes) internal

memory for control databases and frame data

buffer

• Supports jumbo frames up to 4 KBytes

CPU access supports the following interface

options:

• 8/16-bit ISA interface

• Serial interface with MII port; recommended

for light management

• Serial interface in lightly managed mode, or in

unmanaged mode with optional I

C EEPROM

interface

Operates stand-alone or can be cascaded with a

second ZL50410 to reach 16 ports

Ordering Information

ZL50410GDG

ZL50410GDG2

208-Ball LBGA

208-Ball LBGA**

August 2006

**Pb Free Tin/Silver/Copper

-40°C to +85°C

•

Ethernet IEEE 802.3x flow control for full duplex

ports, back pressure flow control for half duplex

ports

Built-in reset logic triggered by system

malfunction

Built-In Self Test for internal SRAM

IEEE-1149.1 (JTAG) test port

•

L2 Switching

•

L2 switching

• MAC address self learning, up to 4 K MAC

addresses

• MAC address table supports unicast and

multicast MAC address and IP multicast

address learning

•

8/16-bit

Serial

ZL50410

MII

GMII / MII

8-Port 10/100M + 1G

Ethernet Switch

EEPROM

10/100/

1000

PHY

RMII / MII / GPSI

Quad

10/100

PHY

Quad

10/100

PHY

Figure 1 - System Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL50410

•

Supports IEEE 802.3ad link aggregation

• Eight (8) groups of up to 8 ports per group

• Allows trunking of ports located on cascaded chip

• Supports load sharing among trunk ports based on:

- Source port

- Source and/or destination MAC address

Traffic Mirroring

• Physical port based (RMII enabled ports only)

• Source or destination MAC address based

• MAC address pair based

Supports module hot swap on all ports

Data Sheet

•

Network Management Support

•

Built-in RMON MIB counters

Description

The ZL50410 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip

provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100/1000 Mbps, and a CPU interface for managed, lightly

managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and up to 4 K

tagged-based Virtual LANs (VLANs). It also supports the Private VLAN Edge feature, allowing the ability to set up

protected ports in a tagged-based VLAN system.

With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50410 provides

powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission

priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission

priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or

the UDP/TCP logical port fields in IP packets. The ZL50410 recognizes a total of 16 UDP/TCP logical ports, 8

hard-wired and 8 programmable (including one programmable range).

The ZL50410 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure

to the CPU. The CPU can then failover that link to an alternate link.

The ZL50410 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port

trunking/load sharing can be used to group ports between interlinked switches to increase the effective network

bandwidth.

In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long

activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50410 also supports a per-system

option to enable flow control for best effort frames, even on QoS-enabled ports.

Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are

collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.

SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network

management solution.

The ZL50410 is fabricated using 0.18 micron technology. The ZL50410 is packaged in a 208-pin Ball Grid Array

package.

Zarlink Semiconductor Inc.

ZL50410

January 2005

•

Data Sheet

•

Updated GMII timing (13.4.11, “Gigabit Media Independent Interface (GMII)“ on page 141)

• reduce min. hold time from 1ns to 0.5ns

• reduced max. output delay by 1ns

Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable

June 2005

•

Corrected ordering code to ZL50410GD”G”

Clarified that port mirroring is only available if the source & destination ports are in RMII mode

Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F

Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap

TSTOUT[0]

Added power sequencing recommendation (1.7, “Power Sequencing“ on page 26)

Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface

(RvGPSI)“ on page 140 and 13.4.12, “MII Management Data Interface (MDIO/MDC)“ on page 143)

Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50410 (11.0, “Hardware Statistics

Counters“ on page 54)

December 2005

•

Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,

“Ball Signal Descriptions“ on page 14)

Added more text to section 2.8, “JTAG“ on page 29

Clarified counter definitions (11.0, “Hardware Statistics Counters“ on page 54)

Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]

Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and

this bit was mistakenly left in the register definition.

April 2006

•

Added Pb-free order code (ZL50410GDG2)

Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 45)

since it wasn’t really discussed in the DS

Clarified registers UCC, MCC & MCCTH

Renamed register UCC (now PCC), as name was misleading

Updated timing to CPU RvMII, as min. output delay should have been 0 ns

July 2006

•

Added typical values to power numbers in “Recommended Operating Conditions” table.

Updated RM6 “CPU_MII_TXEN Output Delay Time” & RM7 “CPU_MII_TXD[3:0] Output Delay Time” max. to

5 ns (old 14 ns)

Zarlink Semiconductor Inc.

ZL50410GDG2 Related Products

	ZL50410GDG2	ZL50410GDG
Description	LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208	Interface Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208
Maker	CONEXANT	CONEXANT
Parts packaging code	BGA	BGA
package instruction	LBGA,	LBGA,
Contacts	208	208
Reach Compliance Code	compli	compliant
JESD-30 code	S-PBGA-B208	S-PBGA-B208
JESD-609 code	e1	e0
length	17 mm	17 mm
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	208	208
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	225
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT	INTERFACE CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN SILVER COPPER	TIN LEAD
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	30
width	17 mm	17 mm

Recommended Resources

OP07-27 pin function diagram

A "desktop theater" based on personal computers

Cheap and beautiful bedside HI-FI-02

L295 principle block diagram and connection circuit

Chopping method reverse bias circuit

Oscillator circuit diagram for debugging

austriamicrosystems authorizes sci-tech telecom as distributor: Siqiang Telecom (Hong Kong) Co., Ltd. has officially signed a distribution cooperation agreement with austriamicrosystems. Siqiang Telecom will authorize the distribution of austriamicrosystems' full ...; rain MCU

Improvement of RC series-parallel frequency-selective network oscillator in El experimental box: What can be improved in this experimental circuit? The teacher said that we can try to improve it from potentiometers, RC series-parallel networks. This is my graduation project, physics, and I don't ...; 张小样张小样 Analogue and Mixed Signal

Texas Instruments helps you solve the three most common problems in high-speed amplifier design!: When designing with high-speed amplifiers, it is important to be familiar with their general specifications and understand their specific concepts. In this article, high-speed amplifiers are operation...; alan000345 Analogue and Mixed Signal

MSP-EXP430F5529 102*64 LCD: I want to use the 102*64 LCD display of MSP-EXP430F5529, but I have never used it before. I wonder if there is any expert who can guide me on how to use it....; 今天下雨了 Microcontroller MCU

LNA [Low Noise Amplifier Practical Application Case]——[qorvo-TQL9092]: This content is originally created by btty038 , a user of EEWORLD forum . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source....; btty038 RF/Wirelessly

A novice asks for advice on STM32 GPIO port register issues: After setting BSRR and BRR to 0 or 1 in the gpio register, why does ODR not have a corresponding change value?...; 月光 stm32/stm8

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components