Advance Data
TSC2L72T18 / TSC2L72T36 / TSC2L72T72
72 Mb Synchronous NBT 3T-iRAM™
Pipelined,
SRAM-Compatible
Features
Error-resistant 3T-iRAM™ technology
NBT (No Bus Turnaround) functionality for zero wait
Read-Write-Read bus usage; fully pin-compatible with
pipelined NtRAM™, NoBL™ and ZBT™
2.5 V ±10% core power supply, 1.8 V or 2.5 V I/O supply
LODRV pin for user-selectable drive strength
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO
pin for Linear or Interleaved Burst mode
Pin-compatible with 2/4/9/18/36Mb devices
Byte write operation (9-bit Bytes)
3 Chip Enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC standard 119- 165- and 209-FBGA packages
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudostatic devices to provide entirely
SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
SRAMs.
The TSC2L72T18/36/72 is a 72Mbit synchronous memory
device that functions much like ZBT, NtRAM, NoBL, and
other pipelined read/double late write SRAMs – it exploits all
available bus bandwidth by eliminating “deselect cycles”
when the device is switched from read to write.
As in all synchronous devices, address, data inputs, and
read/write control inputs are captured on the rising clock
edge. Burst order control (
LBO
) must be tied to a power rail
for proper operation. Asynchronous inputs include the Sleep
mode enable (ZZ) and Output Enable (
G
). Output Enable
can override the synchronous control of the output drivers to
turn them off at any time. Write cycles are internally self-
timed and initiated by the rising clock edge; this eliminates
the complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
The TSC2L72T18/36/72 is pipelined, with a rising-edge-
triggered output register. For read cycles, output data is
stored in the edge-triggered output register during the
access cycle and then released to the output drivers at the
next rising clock edge.
Options
Configurations:
4M x 18
2M x 36
1M x 72
119-FBGA
165-FBGA
209-FBGA
250
200
166
Marking
TSC2L72T18
TSC2L72T36
TSC2L72T72
A
B
C
-250
-200
-166
Packages:
Speed (MHz):
Part number example:
TSC2L72T36A-200
Parameter Synopsis:
tKQ(x18/x36)
tKQ(x72)
3-1-1-1
tCycle
Curr (all)
-250
2.5
3.0
4.0
tbd
-200
3.0
3.0
5.0
tbd
-166
3.5
3.5
6.0
tbd
Unit
ns
ns
ns
mA
Rev. 1.4 – November 14, 2005
Page 1 of 25
©2005, Tezzaron Semiconductor Corp.
Advance Data
TSC2L72T18 / TSC2L72T36 / TSC2L72T72
Pin Descriptions
Symbol
A
0
, A
1
A
DQ
A
, DQ
B
,
DQ
C
, DQ
D
DQ
E
, DQ
F
,
DQ
G
, DQ
H
Type
I
I
I/O
I/O
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
—
I
I
I
Description
Address field LSBs and Address Counter Preset
Inputs
Address Inputs
Data Input and Output pins
Data Input and Output pins
(209-FBGA only)
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os;
active low
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os;
active low (209-FBGA only)
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Low Drive strength control (active high)
Low = High Drive, High = Low Drive
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
(209-FBGA and 165-FBGA only)
Must Connect Low
(209-FBGA only)
Core power supply
I/O and Core Ground
Output driver power supply
BA
,
BB
,
BC
,
BD
BE
,
BF
,
BG
,
BH
NC
CK
CKE
W
E1
,
E3
E2
G
ADV
LODRV
ZZ
LBO
TMS
TDI
TDO
TCK
MCH
MCL
V
DD
V
SS
V
DDQ
Functional Details
Clocking
All inputs
except
Output Enable, Linear Burst Order, and Sleep are synchronized to rising clock edges. Deasserting Clock
Enable (
CKE
high) blocks the Clock input from reaching the RAM’s internal circuits, thus suspending operation. Failure to
observe Clock Enable set-up or hold requirements will result in erratic operation.
Rev. 1.4 – November 14, 2005
Page 5 of 25
©2005, Tezzaron Semiconductor Corp.
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