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TSC2L72T72B-133

Description
DRAM
Categorystorage    storage   
File Size324KB,23 Pages
ManufacturerTezzaron Semiconductor Corp.
Environmental Compliance
Download Datasheet Parametric View All

TSC2L72T72B-133 Overview

DRAM

TSC2L72T72B-133 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerTezzaron Semiconductor Corp.
package instruction,
Reach Compliance Codeunknow
ECCN codeEAR99
Advance Data
TSC2L72T18 / TSC2L72T36 / TSC2L72T72
72 Mb Synchronous NBT 3T-iRAM™
Pipelined,
SRAM-Compatible
Features
ƒ
Error-resistant 3T-iRAM™ technology
ƒ
NBT (No Bus Turnaround) functionality for zero wait
Read-Write-Read bus usage; fully pin-compatible with
pipelined NtRAM™, NoBL™ and ZBT™
ƒ
2.5 V ±10% core power supply, 1.8 V or 2.5 V I/O supply
ƒ
LODRV pin for user-selectable drive strength
ƒ
IEEE 1149.1 JTAG-compatible Boundary Scan
ƒ
LBO
pin for Linear or Interleaved Burst mode
ƒ
Pin-compatible with 2/4/9/18/36Mb devices
ƒ
Byte write operation (9-bit Bytes)
ƒ
3 Chip Enable signals for easy depth expansion
ƒ
ZZ pin for automatic power-down
ƒ
JEDEC-standard 119- 165- or 209-bump BGA package
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudostatic devices to provide entirely
SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
SRAMs.
The TSC2L72T18/36/72 is a 72Mbit synchronous memory
device that functions much like ZBT, NtRAM, NoBL, and
other pipelined read/double late write SRAMs – it exploits all
available bus bandwidth by eliminating “deselect cycles”
when the device is switched from read to write.
As in all synchronous devices, address, data inputs, and
read/write control inputs are captured on the rising clock
edge. Burst order control (
LBO
) must be tied to a power rail
for proper operation. Asynchronous inputs include the Sleep
mode enable (ZZ) and Output Enable (
G
). Output Enable
can override the synchronous control of the output drivers to
turn them off at any time. Write cycles are internally self-
timed and initiated by the rising clock edge; this eliminates
the complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
The TSC2L72T18/36/72 is pipelined, with a rising-edge-
triggered output register. For read cycles, output data is
stored in the edge-triggered output register during the
access cycle and then released to the output drivers at the
next rising clock edge.
Options
ƒ
Configurations:
4M x 18
2M x 36
1M x 72
119-ball BGA
165-ball BGA
209-ball BGA
250
225
200
166
150
133
Marking
TSC2L72T18
TSC2L72T36
TSC2L72T72
A
B
C
-250
-225
-200
-166
-150
-133
ƒ
Packages:
ƒ
Speed (MHz):
Part number example:
TSC2L72T36A-200
Parameter Synopsis:
tKQ(x18/x36)
tKQ(x72)
3-1-1-1
tCycle
Curr (all)
-250
2.5
3.0
4.0
tbd
-225
2.7
3.0
4.4
tbd
-200
3.0
3.0
5.0
tbd
-166
3.5
3.5
6.0
tbd
-150
3.8
3.8
6.7
tbd
-133
4.0
4.0
7.5
tbd
Unit
ns
ns
ns
mA
Rev 1.3 – June 23, 2005
Page 1 of 23
©2005, Tezzaron Semiconductor Corp.
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