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UT54ACTS54-PQCH

Description
AND-OR-Invert Gate, ACT Series, 1-Func, 8-Input, CMOS, CDIP14, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size225KB,9 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

UT54ACTS54-PQCH Overview

AND-OR-Invert Gate, ACT Series, 1-Func, 8-Input, CMOS, CDIP14, SIDE BRAZED, DIP-14

UT54ACTS54-PQCH Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCobham PLC
package instructionDIP, DIP14,.3
Reach Compliance Codeunknow
seriesACT
JESD-30 codeR-CDIP-T14
JESD-609 codee0
length19.43 mm
Logic integrated circuit typeAND-OR-INVERT GATE
MaximumI(ol)0.008 A
Number of functions1
Number of entries8
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Prop。Delay @ Nom-Su16 ns
propagation delay (tpd)16 ns
Certification statusNot Qualified
Schmitt triggerNO
Filter level38535Q/M;38534H;883B
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose1M Rad(Si) V
width7.62 mm
Standard Products
UT54ACS54/UT54ACTS54
4-Wide AND-OR-INVERT Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS54 - SMD 5962-96532
UT54ACTS54 - SMD 5962-96533
DESCRIPTION
The UT54ACS54 and the UT54ACTS54 are 4-wide AND-OR-
INVERT gates. The devices perform the Boolean function:
Y = AB+CD+EF+GH
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUT
A
H
X
X
X
L
X
B
H
X
X
X
X
L
C
X
H
X
X
L
X
D
X
H
X
X
X
L
E
X
X
H
X
L
X
F
X
X
H
X
X
L
G
X
X
X
H
L
X
H
X
X
X
H
X
L
OUTPUT
Y
L
L
L
L
H
H
PINOUTS
14-Pin DIP
Top View
A
C
D
E
F
NC
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B
NC
NC
H
G
Y
14-Lead Flatpack
Top View
A
C
D
E
F
NC
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B
NC
NC
H
G
Y
LOGIC DIAGRAM
A
B
C
D
Y
E
F
LOGIC SYMBOL
A
B
C
D
E
F
G
H
(1)
(13)
(2)
(3)
(4)
(5)
(9)
(10)
&
&
&
>1
G
&
(8)
Y
H
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
1

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