A
PPLICATION
N
OTES AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / SPI bus
X9271
Single Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 100
Ω
typical @ V
CC
= 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 3µA Max
• V
CC
: 2.7V to 5.5V Operation
• 50K
Ω
, 100K
Ω
versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale
Package)
• Low Power CMOS
DESCRIPTION
The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
CC
R
H
SPI
Bus
Interface
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Bus
Interface
and Control
Control
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
50KΩ and 100KΩ
256-taps
POT
V
SS
R
W
R
L
REV 1.2 4/13/04
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Characteristics subject to change without notice.
1 of 23
X9271
DETAILED FUNCTIONAL DIAGRAM
V
CC
Bank 0 Power On Recall
R
0
R
1
HOLD
CS
SCK
SO
SI
A0
A1
WP
WIPER
COUNTER
REGISTER
(WCR)
50KΩ and 100KΩ
256-taps
R
H
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
R
2
R
3
R
L
R
W
Bank 1
R
0
R
1
Bank 2
R
0
R
1
Bank 3
R
0
R
1
R
2
R
3
Control
R
2
R
3
R
2
R
3
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
V
SS
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
REV 1.2 4/13/04
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Characteristics subject to change without notice.
2 of 23
X9271
PIN CONFIGURATION
TSSOP
S0
A0
NC
CS
SCK
SI
V
SS
1
2
3
4
5
6
7
X9271
4
3
2
1
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
HOLD
A1
WP
D
SI
V
SS
WP
A1
B
C
CS
SCK
SO
NC
NC
R
W
A
A0
V
CC
R
L
R
H
NC HOLD
PIN ASSIGNMENTS
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CSP
B3
A4
B2, C2, C3
B4
C4
D4
D3
D2
D1
C1
B1
A1
A2
A3
Symbol
SO
A0
NC
CS
SCK
SI
V
SS
WP
A1
HOLD
R
W
R
H
R
L
V
CC
Serial Data Output.
Device Address.
No Connect.
Chip Select.
Serial Clock.
Serial Data Input.
System Ground.
Hardware Write Protect.
Device Address.
Function
Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.
REV 1.2 4/13/04
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Characteristics subject to change without notice.
3 of 23
X9271
PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
O
UTPUT
(SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
S
ERIAL
I
NPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
S
ERIAL
C
LOCK
(SCK)
The SCK input is used to clock data into and out of the
X9271.
H
OLD
(HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
D
EVICE
A
DDRESS
(A1 - A0)
The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9271.
C
HIP
S
ELECT
(CS)
When CS is HIGH, the X9271 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9271, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
N
O
C
ONNECT
.
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
REV 1.2 4/13/04
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Characteristics subject to change without notice.
4 of 23
X9271
PRINCIPLES OF OPERATION
Device Description
S
ERIAL
I
NTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
A
RRAY
D
ESCRIPTION
The X9271 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
P
OWER
U
P AND
D
OWN
R
ECOMMENDATIONS
.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
≥
V
H
,
V
L
, V
W
. The V
CC
ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
BANK_0 Only
SERIAL
BUS
INPUT
REGISTER 1
(DR1)
8
PARALLEL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
H
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
UP/DN
MODIFIED SCK
UP/DN
CLK
R
L
R
W
REV 1.2 4/13/04
www.xicor.com
Characteristics subject to change without notice.
5 of 23
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