GS8182D37BGD-375T datasheet, PDF

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GS8182D37BGD-375T: DescriptionDDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size549KB，27 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8182D37BGD-375T Overview

DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8182D37BGD-375T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	375 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bi
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.17 A
Minimum standby current	1.7 V
Maximum slew rate	0.635 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

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GS8182D19/37BD-435/400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD)

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

18Mb SigmaQuad-II+

Burst of 4 SRAM

435 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS8182D19/37D SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II B4 RAM is always two address pins

less than the advertised index depth (e.g., the 2M x 8 has a

512K addressable index).

SigmaQuad™ Family Overview

The GS8182D19/37D are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. The GS8182D19/37D SigmaQuad SRAMs are just

Parameter Synopsis

-435

tKHKH

tKHQV

2.3 ns

0.45 ns

-400

2.5 ns

0.45 ns

-375

2.67 ns

0.45 ns

-333

3.3 ns

0.45 ns

-300

3.0 ns

0.45 ns

Rev: 1.03a 11/2011

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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