HFBR-5208M and HFCT-5208M
1 x 9 Fiber Optic Transceivers for 622 Mb/s
ATM/SONET/SDH Applications
Data Sheet
Description
General
The HFBR-5208M (multimode transceiver) and HFCT-
5208M (single-mode transceiver) from Avago
Technolgies allow the system designer to implement a
range of solutions for ATM/SONET STS-12/SDH STM-4
applications.
The overall Avago Technolgies transceiver consists of
three sections: the transmitter and receiver optical
subassemblies, an electrical subassembly and the
mezzanine package housing which incorporates a
duplex SC connector receptacle.
Features
• Performance
HFBR-5208M:
Links of 500 m with 62.5/125 µm multimode fiber
(MMF) from 155-622 Mb/s
HFCT-5208M:
Links of 15 km with 9/125 µm single-mode fiber
(SMF)
• Compliant with ATM forum
622.08 Mb/s physical layer specification (AF-PHY-
0046.000)
• Compliant with ANSI broadband ISDN - physical
layer specification T1.646-1995 and T1.646a-1997
• HFBR-5208M is compliant with ANSI network to
customer installation interfaces - synchronous
optical NETwork (SONET) physical media
dependent specification: multimode fiber
T1.416.01-1998
• HFCT-5208M is compliant to the intermediate
SONET OC12/SDH STM(S4.1) specifications
• Industry-standard multi-sourced 1 x 9 mezzanine
package style
• Single +5 V power supply operation and PECL logic
interfaces
• Wave solder and aqueous wash process compatible
• Unconditionally eye safe laser IEC 825/CDRH Class 1
compliant
Applications
HFBR-5208M:
• General purpose low-cost MMF links at 155 to 650
Mb/s
• ATM 622 Mb/s MMF links from switch-to-switch or
switch-to-server in the end-user premise
• Private MMF interconnections at 622 Mb/s SONET
STS-12/SDH STM-4 rate
HFCT-5208M:
• ATM 622 Mb/s SMF links from switch-to-switch or
switch-to-server in the end-user premise
• Private SMF interconnections at 622 Mb/s SONET
STS-12/SDH STM-4 rate
622 Mb/s Product Family
HFCT-5218M:
• 1300 nm laser-based transceiver in 1 x 9 package
for links of 40 km with single-mode fiber cables
Transmitter Section
The transmitter section of the HFBR-5208M consists of
a 1300 nm LED in an optical subassembly (OSA) which
mates to the multimode fiber cable. The HFCT-5208M
incorporates a 1300 nm Fabry Perot (FP) laser in the
optical subassembly. In addition, this package has been
designed to be compliant with IEC 825 eye-safety
requirements under any single fault condition. The
OSA’s are driven by a custom, silicon bipolar IC which
converts differential PECL logic signals (ECL referenced
to a +5 V supply) into an analog LED/laser drive current.
For example, to operate the HFBR-5208M at a BER of 1 x
10
-12
, the receiver will require an input signal approximately
0.6 dB higher than the -26 dBm level required for 1 x 10
-10
operation, i.e. -25.4 dBm.
An informative graph of a typical, short fiber transceiver
link per-formance can be seen in Figure 2. This figure is
useful for designing short reach links with time-based jitter
requirements. This figure indicates Relative Input Optical
Power versus Sampling Time Position within the receiver
output data eye-opening. The given curves are at a constant
bit-error-ratio (BER) of 10
-10
for four different signaling rates,
155 MBd, 311 MBd, 622 MBd and 650 MBd. These curves,
called “tub” diagrams for their shape, show
the amount of data eye-opening time-width for various
receiver input optical power levels. A wider data eye-
opening provides more time for the clock recovery circuit
to operate within without creating errors. The deeper the
tub is indicates less input optical power is needed to
operate the receiver at the same BER condition. Generally,
the wider and deeper the tub is the better. The Relative
Input Optical Power amount (dB) is referenced to the
absolute level (dBm avg.) given in the Receiver Optical
Characteristics table. The 0 ns sampling time position for
this Figure 2 refers to the center of the Baud interval for the
particular signaling rate. The Baud interval is the reciprocal
of the signaling rate in MBd. For example, at 622 MBd the
Baud interval is 1.61 ns, at 155 MBd the Baud interval is
6.45 ns. Test conditions for this tub diagram are listed in
Figure 2.
The HFBR/HFCT-5208M receiver input optical power
requirements vary slightly over the signaling rate range of
20 MBd to 700 MBd for a constant bit-error-ratio (BER) of
10
-10
condition. Figure 3 illustrates the typical receiver
relative input optical power varies by <0.7 dB over this full
range. This small sensitivity variation allows the optical
budget to remain nearly constant for designs that make
use of the broad signaling rate range of the
HFBR/HFCT-5208M. The curve has been normalized to the
input optical power level (dBm avg.) of the receiver for 622
MBd at center of the Baud interval with a BER of 10
-10
. The
data patterns that can be used at these signaling rates
should be, on average, balanced duty factor of 50%.
Momentary excursions of less or more data duty factor
than 50% can occur, but the overall data pattern must
remain balanced. Unbalanced data duty factor will cause
excessive pulse-width distortion, or worse, bit errors. The
test conditions are listed in Figure 3.
Receiver Section
The receiver contains an InGaAs PIN photodiode mounted
together with a custom, silicon bipolar transimpedance
preamplifier IC in an OSA. This OSA is mated to a custom,
silicon bipolar circuit providing post amplification and
quantization and optical signal detection.
The custom, silicon bipolar circuit includes a Signal Detect
circuit which provides a PECL logic high state output upon
detection of a usable input optical signal level. This single-
ended PECL output is designed to drive a standard PECL
input through normal 50
Ω
PECL load.
Applications Information
Typical BER Performance of HFBR-5208M Receiver versus
Input Optical Power Level
The HFBR/HFCT-5208M transceiver can be operated at
Bit-Error-Ratio conditions other than the required BER = 1
x 10
-10
of the 622 MBd ATM Forum 622.08 Mb/s Physical
Layer Standard and the ANSI T1.646a. The typical trade-off
of BER versus Relative Input Optical Power is shown in
Figure 1. The Relative Input Optical Power in dB is
referenced to the Input Optical Power parameter value in
the Receiver Optical Characteristics table. For better BER
condition than 1 x 10
-10
, more input signal is needed (+dB).
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
LINEAR EXTRAPOLATION OF
10
-4
THROUGH 10
-7
DATA
ACTUAL DATA
BIT ERROR RATIO
-5 -4 -3 -2 -1
0
1
2
3
Figure 1. Relative Input Optical Power -dBm Average.
2
Equivalent Average Optical Input Power in dBm for extrapolated BER =le -10
2.5
2
155.52 MBd
311.04 MBd
622.08 MBd
650.00 MBd
1.5
1
0.5
0
-0.5
-1
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
Clock to Data Offset Delay in nsec (0 = Data Eye Center)
Figure 2. HFBR-5208M Relative Input Optical Power as a function of sampling time position. Normalized to center of Baud interval at
622 MBd. Test Conditions +25°C, 5.25 V, PRBS 2
23
-1, optical
f
= 0.9 ns with 3 m of 62.5 µm MMF.
τ
r
/τ
τ
2.5
Relative Sensitivity in dB for extrapolated BER = le -10
2
HFBR-5208M
HFCT-5208M
1.5
1
0.5
0
-0.5
-1
-1.5
Figure 3. Relative Input Optical Power as a function of data rate normalized to center of Baud interval at 622 MBd.
TestConditions+25°C,5.25V,PRBS2
23
-1,optical
τ
r
/τ
f
=0.9nswith3mofMMForSMF.
τ
3
Recommended Circuit Schematic
When designing the HFBR/HFCT-5208M circuit interface,
there are a few fundamental guidelines to follow. For
example, in the Recommended Circuit Schematic, Figure
4, the differential data lines should be treated as 50 ohm
Microstrip or stripline transmission lines. This will help to
minimize the parasitic inductance and capacitance effects.
Proper termination of the differential data signal will prevent
reflections and ringing which would compromise the signal
fidelity and generate unwanted electrical noise. Locate
termination at the received signal end of the transmission
line. The length of these lines should be kept short and of
equal length to prevent pulse-width distortion from
occurring. For the high-speed signal lines, differential signals
should be used, not single-ended signals. These differential
signals need to be loaded symmetrically to prevent
unbalanced currents from flowing which will cause
distortion in the signal.
In addition to these recommenda-tions, Avago
Technolgies’ Application Engineering staff is available for
consulting on best layout practices with various vendors’
serializer/deserializer, clock recovery/generation integrated
circuits.
Reference Design
Avago Technolgies has developed a reference design for
multimode and single-mode OC-12 ATM-SONET/SDH
applications shown in Figure 6. This reference design uses
a Vitesse Semiconductor Inc.’s VSC8117 clock recovery/
clock generation/serializer/deserializer integrated circuit and
a PMC-Sierra Inc. PM5355 framer IC. Application Note 1178
documents the design, layout, testing and performance of
this reference design. Gerber files, schematic and
application note are available from the Avago Technolgies
web site at the URL of
http://www.avagotech.com
MOUNTING POST
NO INTERNAL CONNECTION
MOUNTING POST
NO INTERNAL CONNECTION
HFBR/HFCT-5208M
TOP VIEW
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL
SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE PECL SIGNALS.
RECOMMEND MULTI-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP OR
STRIPLINE SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 F.
C4 = C7 = 10 F.
L1 = L2 = 1 H COIL OR FERRITE
INDUCTOR (see text comments).
Rx
V
EER
1
RD
2
RD
3
SD
4
Rx
V
CCR
5
Tx
V
CCT
6
TD
7
TD
8
Tx
V
EET
9
C1
C2
V
CC
TERMINATION
AT PHY
DEVICE
INPUTS
C7
V
CC
R5
R7
C6
L1
L2
R2
R1
R3
R4
R6
R8
C3
C4
V
CC
FILTER
AT V
CC
PINS
TRANSCEIVER
R9
R10
C5
TERMINATION
AT TRANSCEIVER
INPUTS
RD
RD
SD
V
CC
TD
TD
Figure 4. Recommended Circuit Schematic for dc Coupling (at +5 V) between Optical Transceiver and Physical Layer IC
4
Operation in -5.2 V Designs
For applications that require -5.2 V dc power supply level
for true ECL logic circuits, the HFBR/HFCT-5208M transceiver
can be operated with a V
CC
= 0 V dc and a V
EE
= -5.2 V dc.
This transceiver is not specified with an operating, negative
power supply voltage. The potential compromises that can
occur with use of -5.2 V dc power are that the absolute
voltage states for V
OH
and V
OL
will be changed slightly due
to the 0.2 V difference in supply levels. Also, noise immunity
may be compromised for the HFBR/HFCT-5208M trans-
ceiver because the ground plane is now the V
CC
supply
point. The suggested power supply filter circuit shown in
the Recommended Circuit Schematic figure should be
located in the V
EE
paths at the transceiver supply pins. Direct
coupling of the differential data signal can be done between
the HFBR-5208M transceiver and the standard ECL circuits.
For guaranteed -5.2 V dc operation, contact your local
Avago Technolgies Component Field Sales Engineer for
assistance.
20.32
(0.800)
2 x 1.9 – 0.1
(0.075 – 0.004)
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is the
control of electromagnetic emissions from electronic
equipment. Success in controlling generated
Electromagnetic Interference (EMI) enables the designer to
pass a governmental agency’s EMI regulatory standard; and
more importantly, it reduces the possibility of interference
to neighboring equipment. There are three options
available for the HFBR/HFCT-5208M with regard to EMI
shielding for providing the designer with a means to
achieve good EMI performance. The EMI performance of
an enclosure using these transceivers is dependent on the
chassis design. Avago Technolgies encourages using
standard RF suppression practices and avoiding poorly EMI-
sealed enclosures. In addition, Avago Technolgies advises
that for the best EMI performance, the metalized case must
be connected to chassis ground using one of the shield
options.
HFBR/HFCT-5208EM transceiver beyond the front surface
of the panel or enclosure is 6.35 mm (0.25 in) . With this
option, there is flexibility of positioning the module to fit
the specific need of the enclosure design. (See Figure 8 for
the mechanical drawing dimensions of this shield.)
The second shielded option, option FM, is for applications
that are designed to have a flush mounting of the module
with respect to the front of the panel or enclosure. The
flush-mount design accommodates a large variety of panel
thickness, i.e. 1.02 mm (.04 in) min to 2.54 mm (0.1 in)
max. Note the reference plane for the flush-mount design
is the interior side of the panel or enclosure. The
recommended distance from the centerline of the
transceiver front solder posts to the inside wall of the panel
is 13.82 mm (0.544 in) . This option contacts the inside
panel or enclosure wall on all four sides of this metal shield.
(See Figure 10 for the mechanical drawing dimensions of
this shield.)
20.32
(0.800)
9 x 0.8 – 0.1
(0.032 – 0.004)
2.54
(0.100)
TOP VIEW
DIM EN SION S ARE IN M ILLIM ETERS (IN CHES)
Figure 5. Recommended Board Layout Pattern
Figure 6. 622.08 Mb/s OC-12 ATM-SONET/SDH Reference Design Board
5
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