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PM25WQ020-EWE

Description
Flash, 256KX8, PDSO8
Categorystorage    storage   
File Size1MB,62 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric View All

PM25WQ020-EWE Overview

Flash, 256KX8, PDSO8

PM25WQ020-EWE Parametric

Parameter NameAttribute value
MakerIntegrated Silicon Solution ( ISSI )
package instructionTSOP, TSOP8,.25
Reach Compliance Codecompli
ECCN codeEAR99
Maximum clock frequency (fCLK)104 MHz
Data retention time - minimum20
Durability100000 Write/Erase Cycles
JESD-30 codeR-PDSO-G8
memory density2097152 bi
Memory IC TypeFLASH
memory width8
Number of terminals8
word count262144 words
character code256000
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
organize256KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialSERIAL
power supply1.8 V
Certification statusNot Qualified
Serial bus typeSPI
Maximum standby current0.00005 A
Maximum slew rate0.015 mA
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
typeNOR TYPE
write protectHARDWARE/SOFTWARE
Pm25WQ020/040
2 Mbit / 4 Mbit bit Single
Operating Voltage Serial Flash
Memory With 104 MHz Dual- or
Quad-Output SPI Bus Interface
Low Power Consumption
-
Max 15 mA active read current
- Max 20 mA program/erase current
-
Max 50uA standby current
Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
Software Write Protection
-
The Block Protect (BP3, BP2, BP1, BP0) bits
allow partial or entire memory to be configured as
read-only
High Product Endurance
- Guaranteed 100,000 program/erase cycles per
single sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin PDIP
- 8-pin 208mil SOIC
- 8-pin 150mil SOIC
- 8-pin 150mil VVSOP
- 8-contact WSON
- 8-contact USON
- 16-pin 300mil SOP
- Lead-free (Pb-free), halogen-free package
Additional 256-byte Security information one-time
programmable (OTP) area
FEATURES
Single Power Supply Operation
- Low voltage range: 1.65 V – 2 V
• Memory Organization
- Pm25WQ020: 256K x 8 (2 Mbit)
- Pm25WQ040: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- 2Mb/4Mb : Uniform 4KByte sectors / Sixteen
uniform 64KByte blocks
Serial Peripheral Interface (SPI) Compatible
- Supports single-, dual- or quad-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 104 MHz clock rate for fast read
- Maximum 208MHz clock rate
- Maximum 416MHz clock rate equivalent Quad SPI
Byte Program Operation
- Typical 8 us/Byte
Page Program (up to 256 Bytes) Operation
- Maximum 1 ms per page program
Sector, Block or Chip Erase Operation
- Sector Erase (4KB)
120ms
(Typ)
- Block Erase (64KB)
250ms
(Typ)
- Chip Erase
(2Mb)
1.5s (Max)
- Chip Erase
(4Mb)
3s (Max)
•Deep
power-down mode
1uA (Typ)
GENERAL DESCRIPTION
The Pm25WQ020/040 are 2Mbit / 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-,
dual or quad-output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104
MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, ranging from
1.65 Volt to 2.0 Volt, to perform read, erase and program operations. The devices can be programmed in
standard EPROM programmers.
The Pm25WQ020/040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These
devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.
The Pm25WQ020/040 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 150mil/208mil, 8-contact WSON, 8-pin PDIP,8-pin VVSOP 150mil and 8-contact WSON
Chingis Technology Corp.
1
DRAFT
Date June, 2012, Rev: 0.4
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