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Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
The Intel 82801BA I/O Controller Hub 2 (ICH2) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
calling 1-800-548-4725 or
by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.
82801BA ICH2
Datasheet
Intel
®
82801BA ICH2 Features
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PCI Bus I/F
— Supports PCI at 33 MHz
— Supports PCI Rev 2.2 Specification
— 133 MByte/sec maximum throughput
— Supports up to 6 master devices on PCI
— One PCI REQ/GNT pair can be given higher
arbitration priority (intended for external
1394 host controller)
Integrated LAN Controller
— WfM 2.0 Compliant
— Interface to discrete LAN Connect
component
— 10/100 Mbit/sec Ethernet support
— 1 Mbit/sec HomePNA* support
Integrated IDE Controller
— Independent timing of up to 4 drives
— Ultra ATA/100/66/33, BMIDE and PIO
modes
— Read transfers up to 100MB/s, Writes to
89 MB/s
— Separate IDE connections for Primary and
Secondary cables
— Implements Write Ping-Pong Buffer for
faster write performance
USB
— 2 UHCI Host Controllers with a total of
4 ports
— USB 1.1 compliant
— Supports wake-up from sleeping states
S1–S4
— Supports legacy Keyboard/Mouse software
AC'97 Link for Audio and Telephony CODECs
— AC’97 2.1 compliant
— Independent bus master logic for 5 channels
(PCM In/Out, Mic Input, Modem In/Out)
— Separate independent PCI functions for
Audio and Modem
— Support for up to six channels of PCM audio
output (full AC3 decode)
— Supports wake-up events
Interrupt Controller
— Support up to 8 PCI interrupt pins
— Supports PCI 2.2 Message-Based Interrupts
— Two cascaded 82C59
— Integrated I/O APIC capability
— 15 interrupts supported in 8259 mode, 24
supported in I/O APIC mode
— Supports Serial Interrupt Protocol
— Supports Front-Side Bus interrupt delivery
1.8 V operation with 3.3 V I/O
— 5V tolerant buffers on IDE, PCI, USB Over-
current and Legacy signals
360-pin EBGA package
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Power Management Logic
— ACPI 1.0 compliant
— ACPI-defined power states (C1–C2, S3–S5)
— ACPI Power Management Timer
— PCI PME# support
— SMI# generation
— All registers readable/restorable for proper
resume from 0V suspend states
— Support for APM-based legacy power
management for non-ACPI Desktop
implementations
External Glue Integration
— Integrated Pull-up, Pull-down and Series
Termination resistors on IDE and processor
interface
Enhanced Hub I/F buffers improve routing
flexibility (Not available with all Memory
Controller Hubs)
Firmware Hub (FWH) I/F supports BIOS
memory size up to 8 MBs
Low Pin count (LPC) I/F
— Allows connection of legacy ISA and X-Bus
devices such as Super I/O
— Supports two Master/DMA devices.
Enhanced DMA Controller
— Two cascaded 8237 DMA controllers
— PCI DMA: Supports PC/PCI — Includes
two PC/PCI REQ#/GNT# pairs
— Supports LPC DMA
— Supports DMA Collection Buffer to provide
Type-F DMA performance for all DMA
channels
Real-Time Clock
— 256-byte battery-backed CMOS RAM
— Hardware implementation to indicate century
rollover
System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon
detection of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
SM Bus
— Host interface allows processor to
communicate via SM Bus
— Slave interface allows an external
Microcontroller to access system resources
— Compatible with most 2-Wire components
that are also I
2
C compatible
Supports ISA bus via external PCI-ISA Bridge
GPIO
— TTL, Open-Drain, Inversion
Timers Based on 82C54
— System timer, Refresh request, Speaker tone
output
The Intel
®
82801BA may contain design defects or errors known as errata which may cause the products to deviate from
published specifications. Current characterized errata are available on request.
82801BA ICH2
Datasheet
iii
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