The AS3LC2M16 is a low-power single transister (IT) CMOS 33,554,432-bit Pseudo Static Random Access Memory (PSRAM)
device organized as 2,097,152 × 16 bits. It is designed for memory applications where slow data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/85 ns are ideal for low-power applications.
The device can be put into deep power down mode with ZZ low and the power consumption at 3.3V is reduced to 33
µ
W. Note
that in deep power down mode the memory cell will not retain its data.
The device can also be put into standby mode when deselected (CS and ZZ high or UB and LB high with ZZ high). The input/
output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS is high , or UB and LB are high),
outputs are disabled (OE High), UB and LB are disabled (UB, LB High), during a write operation ( CS is low and WE Low), or in
power down mode(ZZ is low).
Writing to the device is accomplished by taking Chip Select (CS) Low and Write Enable (WE) input Low. If Byte Low Enable (LB)
is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through
A20). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A20). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Select (CS) and Output Enable (OE) Low while forcing the Write Enable (WE)
High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7.
If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
Max
V
CC
+ 0.5
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2/15/02; V.0.9.9
Alliance Semiconductor
P. 2 of 10
AS3LC2M16
Truth table
CS
H
X
X
L
L
L
ZZ
H
H
L
H
H
H
WE
X
X
X
H
H
H
OE
X
X
X
H
H
L
LB
X
H
X
L
X
L
H
L
L
L
H
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
H
X
X
L
H
L
L
H
L
L
Supply
Current
I
SB
I
SBD
I
CC
I/O0–I/O7 I/O8–I/O15
High Z
High Z
High Z
D
OUT
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Mode
Standby
Deep power down
Output disable
I
CC
High Z
D
OUT
D
IN
Read
I
CC
High Z
D
IN
Write
DC Recommended operating condition (over the operating range)
Parameter
Vcc
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
CC1
Description
Supply voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Average V
CC
Operating Supply
Current at 1 MHz
Test Conditions
-
I
OH
= –1.0mA
I
OL
= 2.1mA
-
-
GND < V
IN
< V
CC
GND < V
O
< V
CC;
Outputs High Z
I
OUT
= 0mA, f=1MHz, CS < 0.2V, ZZ
> V
CC
-0.2V, V
IN
< 0.2V or V
IN
>
V
CC
-0.2V
2.2
–0.2
–1
–1
Min
2.7
2.4
0.4
V
CC
+ 0.2
0.6
+1
+1
5
45 mA at 55 ns
40 mA at 70 ns
35 mA at 85 ns
45 mA at 55 ns
40 mA at 70 ns
35 mA at 85 ns
100
µ
A
Max
3.3
Unit
V
V
V
V
V
µ
A
µ
A
mA
I
CC2
I
OUT
= 0mA, f = f
Max,
Average V
CC
Operating Supply
Current
CS = V
IL
, ZZ = V
IH
, V
IN
= V
IL
or V
IH
I
OUT
= 0mA, t
PC
= min
mA
I
CCP
Page Access Current
CS = V
IL
, ZZ = V
IH
, V
IN
= V
IL
or V
IH
,
page address cycling
CS > V
CC
– 0.2V and ZZ > V
CC
- 0.2V
or UB = LB
> V
cc
-0.2V and ZZ > VCC - 0.2V.
[Other inputs = V
CC
or V
SS
]
ZZ < 0.2V, other inputs = V
CC
or V
SS
mA
I
SB1
Standby Current (CMOS)
Deep Power Down Current;
CMOS Inputs
I
SBD
10
µ
A
2/15/02; V.0.9.9
Alliance Semiconductor
P. 3 of 10
AS3LC2M16
Capacitance
(f = 1 MHz, T
a
= Room temperature, V
CC
= NOMINAL)
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CS, ZZ, WE, OE, LB, UB
I/O
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
Read cycle (over the operating range)
–55
Parameter
Read cycle time
Address access time
Chip select (CS) access time
Output enable (OE) access time
Output hold from address change
CS
ORZ W
o output in low Z
CS high to output in high Z
OE low to output in low Z
UB/LB access time
UB/LB low to low Z
UB/LB high to high Z
OE high to output in high Z
Page cycle time
Page access time
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PC
t
PA
Min
55
–
–
–
10
10
0
5
–
10
0
0
–
–
Max
–
55
55
25
–
–
20
–
55
–
20
20
20
15
70
–
–
–
10
10
0
5
–
10
0
0
–
–
–70
Min
Max
–
70
70
35
–
–
25
–
70
–
25
25
25
20
85
–
–
–
10
10
0
5
–
10
0
0
–
–
–85
Min
Max
–
85
85
35
–
–
25
–
85
–
25
25
25
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
5
4, 5
4, 5
4, 5
3
3
Notes
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
(CS = OE = Low, WE = ZZ = High, UB and /or LB = Low)
t
RC
Address
t
OH
D
OUT
Previous data valid
t
AA
Data valid
t
OH
2/15/02; V.0.9.9
Alliance Semiconductor
P. 4 of 10
AS3LC2M16
Read waveform 2 (CS, OE, UB, LB controlled)
[WE = ZZ = High]
t
RC
Address
t
AA
OE
t
OLZ
CS
t
ACS
t
CLZ
LB, UB
t
BLZ
D
OUT
t
BA
Data valid
t
BHZ
t
OHZ
t
CHZ
t
OE
t
OH
Page waveform 1 (address controlled)
(CS = OE = Low, WE = ZZ = High, UB and /or LB = Low)
I call the pci core of xilinx, I use spatan 3a
How to instantiate Xilinx PCI core? I am using 13.1, and have generated IP. I want to instantiate it into the schematic, but it doesn't work. I want to v...
1. Signal isolation: Its purpose is to isolate the interference source and the part susceptible to interference from the circuit, so that the measurement and control device can only maintain signal co...
I want to learn WINCE embedded development. I am studying .Net and using C# language. I don't know much about WINCE. Please provide me with some introductory books on WINCE....
At present, I have preliminarily browsed the following datesheet, with the aim of having a general idea of the relevant functional modules so that I will know what to use when I encounter them in subs...
[align=center][size=5]Wireless Charging System Design Principle and Implementation[/size][/align] [align=left][size=3] [img=32,32]data:image/png;base64,R0lGODlhIAAgAHcAMSH+GlNvZnR3YXJlOiBNaWNyb3NvZnQg...
Wang Xiaochuan, the "Wudaokou Goalkeeper", is going through a level that he has never gone through before. For example, Sogou's (NYSE: SOGO) financial report, artificial intelligence, and the futur...[Details]
The trade war between China and the United States has become the focus. The United States has begun to play the ban card against Chinese technology companies. The ZTE incident shows that if the ban...[Details]
STM32 uses FSMC to read and write CPLD programs. CPLD is hung on the address line and data line of STM32. CPLD is regarded as an off-chip RAM for reading and writing. On the board I made, CPLD is hun...[Details]
1. Introduction to MC68K CPU The MC683xx series of microcontrollers are composed of the famous MOTOROLA 32-bit microprocessors such as MC68K, 68020, 68040, and the compatible 68K, CPU32, CPU3...[Details]
According to TechRadar, given rumors that
Google
is developing a Pixel Watch
,
the
recently renamed Wear OS
smartwatch
operating system may soon be able to show its full cap...[Details]
When STM32 uses JTMS (PA13) and JTCK (PA14) as normal I/O ports, add the following code before initialization (the order cannot be reversed): RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); G...[Details]
On November 23, Toyota recently released its latest humanoid robot, the T-HR3, which the company said "represents an evolution of the humanoid robot played by previous devices ". This new robot was...[Details]
International Solar Photovoltaic Network News: On November 21, Australia's SMA Solar Technology Co., Ltd. signed a contract with the local government to provide photovoltaic inverters with an insta...[Details]
#include MSP430x12x2.h #define TEM_ADC_CHL 0x0a void InitSys(void); void Read_ADC(unsigned int INCH_channel); void ADC_TO_TEM(void); unsigned int ADC_sample_val; unsigned int long temp1,temp2;...[Details]
MSP430 uses ADC10 to measure the voltage of the temperature diode inside the chip #include "msp430x22x4.h" //This program uses ADC10 to measure the voltage of the temperature diode inside the chip ...[Details]
With the development of human society, people's travel needs are increasing, the number of cars is also increasing, the resulting air pollution problem is becoming more and more serious, and the sa...[Details]
On June 26, 2017, China's new generation of high-speed rail "Fuxing" realized its first two-way service between Shanghai and Beijing, with a maximum speed of 400 kilometers per hour and a standard ...[Details]
On the 25th, Qualcomm held a technology summit in Beijing, inviting almost all important Chinese partners in an extremely rare "show", including SMIC, China Mobile, Lenovo, Xiaomi, OPPO, vivo, ZTE ...[Details]
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
