HI-8435
September 2018
32-Channel Ground/Open or Supply/Open
Sensor with SPI Interface
APPLICATION
·
Avionics Discrete to Digital Sensing
GENERAL DESCRIPTION
The HI-8435 is a 32-channel discrete-to-digital sensor
fabricated with Silicon-on-Insulator (SOI) technology
designed to interface with a Serial Peripheral Interface
(SPI).
Four banks of 8 sense inputs can be programmed as either
GND/Open or Supply/Open sensors. Supply/Open
sensing is also referred to as 28V/Open sensing.
All sense inputs are internally lightning protected to
DO160G, Section 22, Cat AZ, BZ and ZZ without external
components.
The sensing circuit window comparator thresholds are set
by programming the center threshold and hysteresis
registers to values from 2V to 22V. The digital values of the
sensed inputs can be read either one bank at a time or all 4
banks with one command.
Each bank of sensors have a VWETn pin available for
application of a voltage to supply pull up current to the
GND/Open sensor.
Interface to the digital subsystem is simple CMOS logic
inputs and outputs. The logic pins are compatible with 3.3V
logic allowing direct connection to a wide range of
microcontrollers or FPGAs.
PIN CONFIGURATIONS
- VLOGIC
- SCK
- CSN
- SI
- SO
- MRB
- GND
- SENSE_31
- SENSE_30
- SENSE_29
- SENSE_28
VWET0 - 1
SENSE_0 - 2
SENSE_1 - 3
SENSE_2 - 4
SENSE_3 - 5
SENSE_4 - 6
SENSE_5 - 7
SENSE_6 - 8
SENSE_7 - 9
SENSE_8-10
SENSE_9-11
44
43
42
41
40
39
38
37
36
35
34
HI-8435PQI
HI-8435PQT
HI-8435PQM
33 - SENSE_27
32 - VWET3
31 - SENSE_26
30 - SENSE_25
29 - SENSE_24
28 - SENSE_23
27 - SENSE_22
26 - SENSE_21
25 - SENSE_20
24 - SENSE_19
23 - SENSE_18
44 Pin Plastic Quad Flat Pack (PQFP)
10mm x 10mm
44 - VLOGIC
43 - SCK
42 - CSN
41 - SI
40 - SO
39 - MRB
38 - GND
37 - SENSE_31
36 - SENSE_30
35 - SENSE_29
34 - SENSE_28
VWET0 - 1
SENSE_0 - 2
SENSE_1 - 3
SENSE_2 - 4
SENSE_3 - 5
SENSE_4 - 6
SENSE_5 - 7
SENSE_6 - 8
SENSE_7 - 9
SENSE_8 -10
SENSE_9 -11
FEATURES
·
Robust CMOS Silicon-on-Insulator (SOI) technology
·
32-channel Programmable Sense Operation,
VWET1
NC
SENSE_10
SENSE_11
SENSE_12
SENSE_13
SENSE_14
SENSE_15
SENSE_16
SENSE_17
VWET2
- 12
- 13
- 14
- 15
- 16
- 17
- 18
- 19
- 20
- 21
- 22
·
20 MHz Serial Peripheral Interface (SPI)
·
Lightning Protected Sense Inputs
·
Airbus ABD0100H compliant
·
MIL-STD-704 compliant
·
Internal Self-Test
44 Pin Plastic QFN
7mm x 7mm
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8435 Rev. K)
VWET1 - 12
NC - 13
SENSE_10 - 14
SENSE_11 - 15
SENSE_12 - 16
SENSE_13 - 17
SENSE_14 - 18
SENSE_15 - 19
SENSE_16 - 20
SENSE_17 - 21
VWET2 - 22
GND/Open or Supply/Open, 4 X 8 Input Sensors
·
Programmable HI/LO Threshold and Hysteresis in
0.5V steps, from 2V to 22V.
·
Single Low Voltage Supply Operation for low
thresholds applications.
·
Logic Operation from 3.0V to 3.6V
HI-8435PCI
HI-8435PCT
HI-8435PCM
33 - SENSE_27
32 - VWET3
31 - SENSE_26
30 - SENSE_25
29 - SENSE_24
28 - SENSE_23
27 - SENSE_22
26 - SENSE_21
25 - SENSE_20
24 - SENSE_19
23 - SENSE_18
09/18
HI-8435
BLOCK DIAGRAM
VLOGIC
VWET0-3
4
V
LOGIC
MRB
SO_31-0
SI
SO
CSN
SCK
SPI
32
TEST
12
DAC
VALUE/HYSTERESIS
DAC
PSEN_3-0
VREF
4
THRESHOLDS
PU
PD
HI LO HI LO
SO_31-24
SO_23-16
SO_15-8
SO_7-0
8
8
8
8
VWET0
50k
V
LOGIC
PSEN_n
PSEN_n
VTHI/10
V
LOGIC
23.8k
+
-
TESTHI
3.3k
LIGHTNING
PROTECTION
360k
29k
+
TESTLO
VTLO/10
-
PSEN_n
SENSE_7-0
40k
8
SENSE_15-8
8
SENSE_23-16
8
SENSE_31-24
GND
Figure 2.
HOLT INTEGRATED CIRCUITS
2
HI-8435
PIN DESCRIPTIONS
PIN
VLOGIC
VWET<0-3>
FUNCTION
Supply
Supply
DESCRIPTION
3.3V Power Supply for both sensors and logic.
Input to supply current to sense lines in GND/Open operation. Each of the 4
banks of 8 inputs has a VWETn pin. 50kΩ to GND.
4 banks of 8 discrete inputs programmable through the SPI to be either
GND/Open or Supply/Open.
The type of input is programmed by bank, PSEN<3:0> bits. “0” makes the
bank GND/Open sensors, “1” makes the bank SUPPLY/Open sensors
The status of the inputs SENSE<31:0> are stored in SO<31:0>
See SPI section for programming and reading sensors.
0V Ground for Sensor and Logic.
SPI Clock.
SPI Chip Select, Active Low, internal 30kΩ pull-up.
SPI serial data input, internal 30kΩ pull-down.
SPI serial data output.
Master Reset Bar, Active Low, internal 30kΩ pull-up.
Table 1.
SENSE<31:0>
Discrete Input
GND
SCK
CSN
SI
SO
MRB
Supply
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
SPI COMMANDS
OP Code
0x02
0x04
0x3A
0x3C
0x1E
0x82
0x84
0xBA
0xBC
0x9E
0x90
0x92
0x94
0x96
0xF8
R/W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
# Data
Bytes
1
1
2
2
1
1
1
2
2
1
1
1
1
1
4
Write Control Register
Write Program Sense Banks Register, PSEN<3:0>, to program SENSE Inputs
Write GND/Open Threshold Center Value and Hysteresis
Write Supply/Open Threshold Center Value and Hysteresis
Write Test Mode Data Register
Read Control Register
Read Program Sense Banks Register, to read programmed bank type
Read GND/Open Threshold Center Value and Hysteresis
Read Supply/Open Threshold Center Value and Hysteresis
Read Test Mode Data Register
Read Bank 0, SOUT Register, SO<7:0>, status of SENSE<7:0> Inputs
Read Bank 1, SOUT Register, SO<15:8>, status of SENSE<15:8> Inputs
Read Bank 2, SOUT Register, SO<23:16>, status of SENSE<23:16> Inputs
Read Bank 3, SOUT Register, SO<31:24>, status of SENSE<31:24> Inputs
Read All Banks, SOUT Register, SO<31:0>, status of SENSE<31:0> Inputs
Table 2.
HOLT INTEGRATED CIRCUITS
3
DESCRIPTION
HI-8435
SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS
The HI-8435 uses a SPI (Serial Peripheral Interface) for host
access to internal registers which program the chip and store
sensor status. Host serial communication is enabled through
the active low, Chip Select (CSN) pin, and is accessed via a
four-wire interface consisting of Serial Data Input (SI) from the
host, Serial Data Output (SO) to the host, the Serial Clock
(SCK) and the CSN. All read / write cycles are completely self-
timed.
The SPI protocol specifies master and slave operation; the
HI-8435 operates as a SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-8435 operates in
Mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic must be set for Mode 0 for proper
communications with the HI-8435.
As seen in Figure 3, SPI Mode 0 holds SCK in the low state
when idle. The SPI protocol transfers serial data in 8-bit bytes.
Once CSN is asserted, the rising edge of SCK shifts the input
data into the master and slave devices, starting with each byte's
most-significant bit. A rising edge on CSN completes the serial
transfer and re-initializes the HI-8435 SPI for the next transfer.
If CSN goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex), per Figure 3 below.
However the HI-8435 operates half duplex, maintaining high
impedance on the SO output, except when actually transmitting
serial data. When the HI-8435 is sending data on SO during
read operations, activity on its SI input is ignored. The host
likewise ignores its SI input activity while transmitting to the HI-
8435.
HI-8435 SPI INSTRUCTIONS
The SPI Instructions used to read, write and configure the
HI-8435 consist of an opcode and data bytes. Each SPI
instruction begins with an 8-bit opcode with the format shown
below. The most significant bit (MSB) specifies whether the
instruction is a write, “0”, or a read, “1”, transfer.
When CSN goes low, the first 8 rising edges of the SCK shift the
op code into the decoder register, MSB first. The SPI can be
clocked up to 20 MHz.
/W
R
X
MSB
7
6
X
5
X
4
X
3
X
2
X
1
X
0
LSB
Figure 4. SPI OPCODE FORMAT
For write instructions, the next 8 rising SCK edges shift a data
byte into the buffer register. The specific instruction register is
loaded on the 8th rising SCK edge. This sequence is repeated
until the required number of data bytes for the instruction are
written.
For read instructions, the most significant bit of the requested
data word appears at the SO pin at the next falling SCK edge
after the last op code bit is clocked into the decoder. As in write
instructions, the number of data bytes varies with read the
instruction. SO data changes on the falling SCK edges.
Figure 5 to Figure 7 show read and write timing for single-byte,
dual-byte and four byte register operations. The instruction op
code is immediately followed by data bytes comprising the 8-bit
data bytes read or written. For a register read or write, CSN is
negated after all data bytes are transferred.
Table 2 summarizes the HI-8435 SPI instruction set.
SCK
(SPI Mode 0)
SI
SO
CSN
High Z
MSB
MSB
LSB
LSB
High Z
FIGURE 3. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
HOLT INTEGRATED CIRCUITS
4
HI-8435
Note:
SPI Instruction op-codes not shown in Table 2 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to a read instruction.
Two instruction bytes cannot be “chained”; CSN must be
negated after each instruction, and then reasserted for the
following Read or Write instruction.
0
SCK
MSB
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LSB
SI
Op-Code Byte
SO
High Z
Data Byte 0
CSN
MSB
LSB
High Z
FIGURE 5. Single-Byte Read From a Register
0
SCK
SPI Mode 0
MSB
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LSB MSB
LSB MSB
LSB
SI
Op-Code Byte
SO
High Z
Data Byte 1
Data Byte 0
CSN
FIGURE 6. 2-Byte SPI Write Example
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK
SPI Mode 0
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
SI
Op-Code Byte
SO
High Z
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
CSN
FIGURE 7. 4-Byte SPI Read Example
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