NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = +0.4V, max Logic “1” = 2.4V min.
(2) Adjustable to zero. (3) FSR means Full Scale Range. For example, unit connected for
±10V
range has 20V FSR. (4) Conversion time may be shortened with
“Short Cycle” set for lower resolution, see “Additional Connections Required” section. (5) See Table I. CSB = Complementary Straight Binary. COB = Complementary
NOTE: (1) Metal lid of package is connected to pin 22 (Analog Common).
ABSOLUTE MAXIMUM SPECIFICATIONS
+V
CC
to Common .................................................................... 0 to +16.5V
–V
CC
to Common .................................................................. 0V to –16.5V
+V
DD
to Common ....................................................................... 0V to +7V
Analog Common to Digital Common ...............................................
±0.5V
Logic Inputs to Common ........................................................... 0V to V
DD
Maximum Power Dissipation ....................................................... 1000mW
Lead Temperature (10s) .................................................................. 300°C
PACKAGE INFORMATION
MODEL
ADC71JG
ADC71KG
ADC71AG
ADC71BG
PACKAGE
32-Pin
32-Pin
32-Pin
32-Pin
Hermetic
Hermetic
Hermetic
Hermetic
DIP
DIP
DIP
DIP
PACKAGE DRAWING
NUMBER
(1)
172-5
172-5
172-5
172-5
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
MODEL
ADC71JG
ADC71KG
ADC71AG
ADC71BG
TEMPERATURE RANGE
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
NONLINEARITY
±0.006%
±0.003%
±0.006%
±0.003%
FSR
FSR
FSR
FSR
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADC71
Convert Command
(1)
Maximum Throughput Time
(2)
Conversion Time
Internal Clock
Status (EOC)
MBS
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Serial Data Out
MSB
1
“0”
2
“1”
3
“1”
4
“0”
5
“0”
6
“1”
7
“1”
8
“1”
9
“0”
10
“1”
11
“1”
12
“0”
13
“1”
“0”
“1”
“1”
“0”
“0”
“1”
“1”
“1”
“0”
“1”
“1”
“0”
“1”
“0”
“0”
LSB
14
“0”
15
“0”
“1”
16
“1”
NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is initiated
by the “trailing edge” of the convert command. (2) 57µs for 16 bits.
FIGURE 1. ADC71 Timing Diagram.
Serial
Out
40-125ns
40-125ns
Bit 16
Bit 16
Valid
Clock
Out
Status
40-125ns
FIGURE 2. Timing Relationship of Serial Data to Clock.
Binary (BIN)
Output
Analog Input
Voltage Range
Code
Designation
One Least
Significant
Bit (LSB)
FSR
2
n
n = 12
n = 13
n = 14
Defined As:
±10V
COB
(1)
or CTC
(2)
20V
2
n
4.88mV
2.44mV
1.22mV
FIGURE 3. Timing Relationship of Valid Data to Status.
INPUT VOLTAGE RANGE AND LSB VALUES
±5V
COB
(1)
or CTC
(2)
10V
2
n
2.44mV
1.22mV
610µV
±2.5V
COB
(1)
or CTC
(2)
5V
2
n
1.22mV
610µV
305µV
CSB
(3)
10V
2
n
2.44mV
1.22mV
610µV
CSB
(3)
5V
2
n
1.22mV
610µV
305µV
CSB
(3)
20V
2
n
4.88mV
2.44mV
1.22mV
0 to +10V
0 to +5V
0 to +20V
Transition Values
MSB LSB
000 ... 000
(4)
011 ... 111
111 ... 110
+Full Scale
Mid Scale
–Full Scale
+10V–3/2LSB
0
–10V +1/2LSB
+5V–3/2LSB
0
–5V +1/2LSB
+2.5V–3/2LSB
0
–2.5V +1/2LSB
+10V–3/2LSB
+5V
0 +1/2LSB
+5V–3/2LSB
+2.5V
0 +1/2LSB
+20V–3/2LSB
+10V
0 +1/2LSB
NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Two’s Complement—obtained by inverting the most significant bit MSB (pin 1). (3) CSB
= Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.
TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions.
®
ADC71
4
TYPICAL PERFORMANCE CURVES
At +25°C and rated power supplies unless otherwise noted.
GAIN DRIFT ERROR (% OF FSR)
vs TEMPERATURE
+0.10
+0.08
ADC71AG, BG
ADC71JG,KG
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
% of FSR Error per % of Change In V
SUPPLY
0.1
0.06
0.04
0.02
0.01
0.006
0.004
0.002
0.001
1
10
100
1k
Frequency (Hz)
10k
100k
+5VDC
+15VDC
–15VDC
Gain Drift Error (% of FSR)
+0.06
+0.04
+0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–25°C
0°C
+25°C
Temperature (°C)
+70°C +85°C
DISCUSSION OF
PERFORMANCE
The accuracy of a successive approximation A/D converter
is described by the transfer function shown in Figure 1. All
successive approximation A/D converters have an inherent
Quantization Error of
±1/2
LSB. The remaining errors in the
A/D converter are combinations of analog errors due to the
linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including Gain, Offset, Linearity, Differential Linear-
ity, and Power Supply Sensitivity. Initial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature
rotates the line (Figure 1) about the zero or minus full scale
point (all bits Off) and Offset drift shifts the line left or right
over the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of A/D
NOTE: Pages 4&5
were switched for
Abridged Version
for '96 data book.
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
level over the range of the A/D converter. A Differential
Linearity error of
±1/2
LSB means that the width of each bit
step over the range of the A/D converter is 1 LSB,
±1/2
LSB.
The ADC71 is monotonic, assuring that the output digital
code either increases or remains the same for increasing
analog input signals. Burr-Brown guarantees that these con-
verters will have no missing codes over a specified tempera-
ture range when short-cycled for 14-bit operation.
TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input such
that the positive true digital word 1001 1000 1001 0110
exists. The output will be complementary as shown in Figure
2 (0110 0111 0110 1001 is the digital output). Figures 3 and
4 are timing diagrams showing the relationship of serial data
to clock and valid data to status.
DEFINITION OF DIGITAL CODES
Parallel Data
Two binary codes are available on the ADC71 parallel
output; they are complementary (logic “0” is true) straight
binary (CSB) for unipolar input signal ranges and comple-
mentary offset binary (COB) for bipolar input signal ranges.
Complementary two’s complement (CTC) may be obtained
by inverting MSB (Pin 1).
Table I shows the LSB, transition values, and code defini-
tions for each possible analog input signal range for 12-, 13-
and 14-bit resolutions. Figure 5 shows the connections for
14-bit resolution, parallel data output, with
±10V
input.
0000 ... 0000
Digital Output (COB Code)
(1)
All Bits On
Gain
Error
–1/2LSB
0000 ... 0001
0111 ... 1101
0111 ... 1110
0111 ... 1111
1000 ... 0000
1000 ... 0001
1111 ... 1110
1111 ... 1111
–FSR/2
e
IN
Off
All Bits Off
Offset
Error
+1/2LSB
e
IN
On
Analog Input
+FSR/2–1LSB
NOTE: (1) See Table I for Digital Code Definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar A/ D
京公网安备 11010802033920号
EEWORLD
