CLTI-67201V-65 datasheet, PDF - EEWORLD Datasheet

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CLTI-67201V-65: DescriptionFIFO, 512X9, 65ns, Asynchronous, CMOS, PDSO28,; Categorystorage storage; File Size159KB，16 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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CLTI-67201V-65 Overview

FIFO, 512X9, 65ns, Asynchronous, CMOS, PDSO28,

CLTI-67201V-65 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	TEMIC
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	65 ns
Maximum clock frequency (fCLK)	12.5 MHz
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
Memory IC Type	OTHER FIFO
memory width	9
Number of terminals	28
word count	512 words
character code	512
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512X9
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP28,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.000004 A
Maximum slew rate	0.06 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL

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MATRA MHS

L 67201/L 67202

512

9 & 1K

9 / 3.3 Volts CMOS Parallel FIFO

Introduction

The L67201/202 implement a first-in first-out algorithm,

featuring asynchronous read/write operations. The FULL

and EMPTY flags prevent data overflow and underflow.

The Expansion logic allows unlimited expansion in word

size and depth with no timing penalties. Twin address

pointers automatically generate internal read and write

addresses, and no external address information are

required for the MHS FIFOs. Address pointers are

automatically incremented with the write pin and read

pin. The 9 bits wide data are used in data communications

applications where a parity bit for error checking is

necessary. The Retransmit pin reset the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Using an array of eight transistors (8 T) memory cell and

fabricated with the state of the art 1.0

µm

lithography

named SCMOS, the L 67201/202 combine an extremely

low standby supply current (typ = 1.0

µA)

with a fast

access time at 55 ns over the full temperature range. All

versions offer battery backup data retention capability

with a typical power consumption at less than 5

µW.

For military/space applications that demand superior

levels of performance and reliability the L 67201/202 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

First-in first-out dual port memory

Single supply 3.3

0.3 volts

512

9 organisation (L 67201)

1024

9 organisation (L 67202)

Fast access time

55, 60, 65 ns, commercial, industrial military and

automotive

Wide temperature range :

– 55

°C

to + 125

°C

67201L/202L low power

67201V/202V very low power

Fully expandable by word width or depth

Asynchronous read/write operations

Empty, full and half flags in single device mode

Retransmit capability

Bi-directional applications

Battery back-up operation 2 V data retention

TTL compatible

High performance SCMOS technology

Rev. C (10/11/95)

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