W.A.R.P. 1.1
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 Input Configurable Variables
Up to 16 Membership Functions for an Input
Variable
Up to 16 Output Variables
Up to 128 Membership Functions for all
Consequents
MAX-DOT Inference Method
Defuzzification on chip
Software Tools and Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integrated structure with high inferencing perform-
ances and flexibility. To get those results a modular
architecture based on a set of parallel memory
blocks has been implemented.
In order to obtainhigh performances W.A.R.P. uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
ented strategy to store the AntecedentMembership
Table 1. W.A.R.P. Configuration Settings
Number of Inputs
Standard Rule Format
Rules Number
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [1..8]
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4 Antecedent, 1 Consequent format
Configurable [up to 16 for an input variable]
Max 256 for all outputs variables
8 bit
8 bit
CPGA 100
PLCC84
Figure 1. Logic Diagram
MCLK VS S VDD
FIN
S YNC
8
10
O0-O9
4
I0-I7
3
W.A.R.P.
1.1
OCNT0-OCNT3
STB
NP
EP
EPA0-EPA2
10
A0-A9
CHM OFL PRS T
May 1996
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/19
W.A.R.P.1.1
Figure 2. CPGA100 Pin Configuration
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
O
I
OL
I
OH
T
OPT
T
STG
Notes:
Parameter
Supply Voltage
Input Voltage
Ouput Voltage
Output Sink Peak Current
Output Source Peak Current
Operating Temperature
Storage Temperature (Ceramic)
Storage Temperature (Plastic)
Value
-0.5 to 7
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
+24
-12
0 to +70
-65 to +150
-45 to +125
Unit
V
V
V
mA
mA
°C
°C
°C
Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
2/19
W.A.R.P.1.1
Figure 3. PLCC84 Pin Configuration
EPA0
EPA1
EPA2
VDD
VDD
A9
VDD
VSS
VSS
11 10 9
12
VSS
VDD
MCLK
I0
I1
I2
I3
I4
I5
I6
I7
CHM
FIN
OFL
PRST
TE
MTE
VSS
VDD
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
SYNC
OTST
OMTS
STB
EP
VSS
NP
OCNT3
OCNT2
OCNT1
OCNT0
VSS
VDD
VSS
VDD
W.A.R.P. 1.1
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
64
63
62
61
60
59
58
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
VDD
VDD
VSS
VSS
VSS
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
Table 3. Recomended Operation Conditions (Ta=0 to +70
°C
unless otherwise specified)
Symbol
V
DD
V
IL
V
IH
V
OL
V
OH
FCLK
CL
Parameter
Supply Voltage
Input Voltage
Input Voltage
Ouput Voltage
Ouput Voltage
Clock Frequency
Output Load Capacitance
10
2.4
40
85
2
0.5
Min
4.75
Typ
5.0
Max
5.25
0.8
Unit
V
V
V
V
V
MHz
pF
3/19
W.A.R.P.1.1
Table 4. Pin Description
Name
V
DD
V
SS
A0-A9
I0-I7
PRST
FIN
OFL
CHM
TE
MTE
MCLK
EPA0-EPA2
O0-O9
OCNT0-OCNT3
STB
EP
NP
OTST
OMTS
SYNC
*
Pins Type
-
-
I/O
I
I
I
I
I
I
I
I
*
Function
Power Supply
Ground
Memory Address Bus
Data Input Bus
Preset
First Input Signal
Off-Line/On-Line Switch
Charge Mode Switch
Testing (it must be connected to V
SS
)
Testing (it must be connected to V
SS
)
Clock (up to 40 MHz)
EPROM Address Bus
Defuzzified Output
Output Counter
Strobe (Output Ready Signal)
End Process
New Process
Testing (it must be connected to V
SS
)
Testing (it must be connected to V
SS
)
External Synchronization
O
O
O
O
O
O
O
O
O
Pins not used in W.A.R.P. 1.0
Functions in dedicated memories in order to reduce
the computational time. Therefore a great amount
of W.A.R.P. processing is based on a look-up table
approach rather than on on-line calculation.
Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 2
6
or 2
7
elements, are stored in four internal RAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area and its barycentre. This is due
to the adoption of the Center of Gravity defuzzifica-
tion method.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
course and MF shapes. During this phase W.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
program memory. This microcode, which drives the
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adopted configuration. The possible configurations
are shown in table 1.
During the on-line phase (up to 40MHz working
frequency), W.A.R.P. processes the input data and
produces its outputs according to the configuration
loaded in the downloading phase.
W.A.R.P. is conceived to work together with tradi-
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsible for all the fuzzy related computing.
W.A.R.P. is manufactured using the high perform-
ance, reliable HCMOS4T (O.7µm) SGS-THOM-
SON Microelectronics process.
PIN DESCRIPTION
V
DD
, V
SS
: Power is supplied to W.A.R.P. using
these pins. V
DD
is the power connectionand V
SS
is
the ground connection; multi-connections are nec-
essary.
A0-A9:
When the CHM pin is
low
they accept as
input the addresses for the internal memory bus. In
the off-line mode they are used to address W.A.R.P.
memories where the microprogram and data of
antecedent and consequentmembership functions
must be loaded.
Each A0-A9 word is composed by assembling the
data contained in the memory support related to .cs
and .add files (see W.A.R.P.-SDT User Manual). In
particular, couples of data respectively coming from
.cs and .add files are joined to form a single A0-A9
word in the following way:
4/19
W.A.R.P.1.1
must be sent to W.A.R.P. from the outside by
means of the input pins A0-A9.
When CHM is
high
W.A.R.P. automatically gener-
ates the addresses of its internal memories and
manages the EPROMs reading by means of the
addresses contained in EPA0-EPA2 and A0-A9
output pins (13 bits).
TE:
For testing purpose only. It must be connected
to V
SS
.
MTE:
For testing purpose only. It must be con-
nected to V
SS
.
MCLK:
This is the input master clock whose fre-
quency can reach up to 40MHz (MAX).
During the off-line phase with CHM
high,
the
DCLK signal with a frequency of MCLK/32 is gen-
erated in order to drive the downloading phase
timing.
EPA0-EPA2:
During the off-line phase and in cor-
respondencewith CHM
high,
these output pins are
joined (as MSB) to A0-A9 to obtaine the complete
address of the memory support where to read the
data to be loaded in W.A.R.P. internal memories.
EPA0-EPA2 are not used when CHM is
low
or in
W.A.R.P. 1.0 release.
O0-O9:
These pins carry out the output values.
When the STB (strobe pin) is
high,
one output
variable can be read by external devices (in on-line
mode). The resolution of output variables is 1024
points (10 bits). If there are more than one output,
the output variables are calculated one by one and
they are provided in the sequence stabilized during
the editing phase (see W.A.R.P.-SDT User Man-
ual).
OCNT0-OCNT3:
This 4 bit output bus provides the
output variables with a progressive number during
the on-line phase. As a consequenceit is possible
to know to which variable correspond the data that
are on the output data bus (O0-O9). The dimension
of OCNT bus is connected with the maximum
number of output variables (16).
STB:
The strobe pin enables the user to utilize the
output. When this pin is
high
it indicates that a new
output variable has been calculated and it is ready
on the output bus (O0-O9). This signal synchro-
nizes the external devices and in particular the
interfaces with the controlled processes (on-line
mode).
EP:
This signal
low
indicates that the processing
of all the rules has been completed.
NP:
This output pin indicates that a new process
can start. NP is automatically set
low
before the
last output has been calculated, so that it is possible
to start a new data acquisition before (with a new
FIN) the computation is terminated.
add7
add6 add5 add4 add3 add2 add1 add0
cs7
cs6
cs5
cs4 cs3
cs2
cs1
cs0
cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0
A9
A0
This resulting word allows to identify the appropri-
ate memory [cs2-cs0] and its respective address
[add6-add0] where the relative I0-I7 are to be
stored.
When the CHM pin is
high,
during the off-line
phase, W.A.R.P. generates the addresses for its
internal memories and send those addresses to the
single external memory support where data (.dat
file) are located. These addresses, which are sent
by means of the EPA0-EPA2 and A0-A9 (EPA0
MSB, A9 LSB) output pins, allow to identify the
data (on the EPROM) that have be loaded in
W.A.R.P. internal memories.
In on-line mode A0-A9 are not used.
I0-I7:
During the off-line phase these 8 data input
pins accept the microcode configuration and data
to be written into the internal memories. The ante-
cedent memory word size is 64 bits, so it is neces-
sary to give each word 8 bits at a time. In the same
way are written the words of consequent memory
and of program memory.
In on-line mode this bus carries the input variables
to W.A.R.P.. Input values have a resolution of 6 or
7 bits in accordance with the configuration setting.
PRST:
This is the restart pin of W.A.R.P.. It is
possible to restart the work during the computation
(on-line phase) or before the writing of internal
memories (off-line phase). In both cases it must be
put
low
at least for a clock period.
FIN:
During the on-line phase it will start the run-
time acquisition cycle. This pin is activated by
providing a positive pulse for a time no lower than
an entire clock period. When all expected inputs
have been processed, a new FIN pulse must be
sent to activate a new process.
OFL:
When this pin is
high,
the chip is enabled to
load data in the internal RAMs (off-line phase). It
must be
low
when the fuzzy controller is waiting for
input values and during the processing phase (on-
line phase).
CHM:This
pin, which is used only during the off-line
phase, determines the charge mode. CHM is not
present in W.A.R.P. 1.0 release.
When CHM is
low
the addresses of the internal
memory locations where data have to be stored
5/19
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