STE53NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
ST E53NA50
V
DSS
500 V
R
DS(on)
< 0.085
Ω
I
D
53 A
s
s
s
s
s
s
s
s
s
TYPICAL R
DS(on)
= 0.075
Ω
HIGH CURRENT POWER MODULE
AVALANCHE RUGGED TECHNOLOGY
VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY
EASY TO MOUNT
SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS
EXTREMELY LOW Rth (Junction to case)
VERY LOW INTERNAL PARASITIC
INDUCTANCE
ISOLATED PACKAGE UL RECOGNIZED
ISOTOP
APPLICATIONS
s
SMPS & UPS
s
MOTOR CONTROL
s
WELDING EQUIPMENT
s
OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(•)
P
to t
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 kΩ)
Gate-source Voltage
Drain Current (continuous) at T
c
= 25 C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
Total Dissipation at T
c
= 25 C
Derating Factor
T
st g
T
j
V
ISO
Storage Temperature
Max. Operating Junction T emperature
Insulation W ithhstand Voltage (AC-RMS)
o
o
Value
500
500
±
30
53
33
212
460
3.68
-55 to 150
150
2500
Unit
V
V
V
A
A
A
W
W/
o
C
o
o
C
C
V
1/7
(•) Pulse width limited by safe operating area
February 1998
STE53NA50
THERMAL DATA
R
t hj-ca se
R
thc -h
Thermal Resistance Junction-case
Thermal Resistance Case-heatsink W ith Conductive
Grease Applied
Max
Max
0.27
0.05
o
o
C/W
C/W
AVALANCHE CHARACTERISTICS
Symb ol
I
AR
E
AS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max,
δ
< 1%)
Single Pulse Avalanche Energy
o
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
Max Valu e
26
1014
Unit
A
mJ
ELECTRICAL CHARACTERISTICS
(T
case
= 25
o
C unless otherwise specified)
OFF
Symb ol
V
(BR)DSS
I
DSS
I
GSS
Parameter
Drain-source
Breakdown Voltage
I
D
= 1 mA
Test Cond ition s
V
GS
= 0
Min.
500
100
1000
±
400
Typ .
Max.
Un it
V
µA
µA
nA
V
DS
= Max Rating
Zero G ate Voltage
Drain Current (V
GS
= 0) V
DS
= Max Rating
Gate-body Leakage
Current (V
DS
= 0)
V
GS
=
±
30 V
T
c
= 125 C
o
ON (∗)
Symb ol
V
GS(th)
R
DS( on)
I
D(o n)
Parameter
Gate Threshold
Voltage
V
DS
= V
GS
Test Cond ition s
I
D
= 1 mA
I
D
= 27 A
53
Min.
2.25
Typ .
3
0.075
Max.
3.75
0.085
Un it
V
Ω
A
Static Drain-source On V
GS
= 10V
Resistance
On State Drain Current V
DS
> I
D(on)
x R
DS(on) max
V
GS
= 10 V
DYNAMIC
Symb ol
g
fs
(∗)
C
iss
C
oss
C
rss
Parameter
Forward
Transconductance
Input Capacitance
Output Capacitance
Reverse T ransfer
Capacitance
Test Cond ition s
V
DS
>I
D(on )
X
V
DS
= 25 V
RDS(on)MAX
Min.
25
Typ .
Max.
Un it
S
I
D
= 27 A
V
GS
= 0
f = 1 MHz
13
1500
450
16
2000
650
nF
pF
pF
2/7
STE53NA50
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
Symb ol
t
d(on)
t
r
Q
g
Q
gs
Q
gd
Parameter
Turn-on Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Cond ition s
V
DD
= 250 V I
D
= 27 A
V
GS
= 10 V
R
G
= 4.7
Ω
(see test circuit, figure 1)
V
DD
= 400 V
I
D
= 53 A V
GS
= 10 V
Min.
Typ .
57
92
470
54
219
Max.
80
130
658
Un it
ns
ns
nC
nC
nC
SWITCHING OFF
Symb ol
t
r(Vof f)
t
f
t
c
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Cond ition s
V
DD
= 400 V
I
D
= 53 A
V
GS
= 10 V
R
G
= 4.7
Ω
(see test circuit, figure 3)
Min.
Typ .
105
36
145
Max.
145
50
205
Un it
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
I
SD
I
SDM
(•)
V
SD
(∗)
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
SD
= 53 A
V
GS
= 0
1000
31.5
63
Test Cond ition s
Min.
Typ .
Max.
53
212
1.6
Un it
A
A
V
ns
µC
A
I
SD
= 53 A di/dt = 100 A/µs
o
T
j
= 150 C
V
R
= 100 V
(see test circuit, figure 3)
(∗) Pulsed: Pulse duration = 300
µs,
duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area for
Thermal Impedance
3/7
STE53NA50
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/7
STE53NA50
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Fig. 1:
Switching Times Test Circuits For
Resistive Load
Fig. 2:
Gate Charge test Circuit
Fig. 3:
Test Circuit For Inductive Load Switching
And Diode Recovery Times
5/7
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