PWR-82520
3-PHASE DC MOTOR TORQUE
CONTROLLER
DESCRIPTION
The PWR-82520 is a high-perfor-
mance current-regulating torque loop
controller. It is designed to accurate-
ly regulate the current in the windings
of 3-phase brushless DC and brush
DC motors.
The PWR-82520 is a completely self-
contained motor controller that con-
verts the analog input command sig-
nal into motor current and uses the
signals from Hall-effect sensors in the
motor to commutate the current in the
motor windings. The motor current is
internally sensed and processed into
an analog signal. This signal is
summed together with the command
signal to produce an error signal that
controls the pulse width modulation
(PWM) duty cycle of the output, thus
controlling the motor current. The
PWR-82520 can be tuned by using
an external Proportional-Integral (PI)
regulator network in conjunction with
the internal error amplifier.
FEATURES
•
100V Rating for 28V Motors
•
10 Amp Continuous Output Current
•
Complementary Four-Quadrant
•
•
•
•
•
•
•
Operation
3% Linearity Accuracy
5% Current Regulating Accuracy
User-Programmable Compensation
10 kHz - 50 kHz PWM Frequency
Operates as Current or Voltage
Controller
Self-Contained 3-Phase Motor
Controller
Built-in Current Limit
APPLICATIONS
Packaged in a small DIP-style hybrid,
the PWR-82520 are ideal for applica-
tions with limited printed circuit board
area.
The PWR-82520 is ideal for applica-
tion requiring current regulation
and/or holding torque at zero input
command.
System applications
include flight surface control on air-
craft for horizontal stabilizers and
flaps, missile fin control, fuel and
hydraulic pumps, radar and counter-
measures systems.
5.0V
10K 10K 10K
HALL A
HALL B
HALL C
+15V HALL SUPPLY OUTPUT
HALL SUPPLY GND
COMMAND OUT
COMMAND IN +
COMMAND IN -
39
38
37
40
41
33
10K
31
30
10K
10K
10K
COMMAND GND
29
-
+
HA
HB
HC
+15V
VBUS+
4,5,6
100
COMMAND
BUFFER
5.0V
DRIVE
A
PHASE A
PHASE A
14,15,16
COMMUTATION
LOGIC
CASE GND
ENABLE
+15V SUPPLY
GROUND
-15V SUPPLY
PWM IN
17
36
28
27
26
19
20
22
21
32
34
CASE
10K
PWM
LOGIC
CIRCUITRY
V
DD
DRIVE
B
PHASE B
PHASE B
7,8,9
+
+
V
EE
DRIVE
C
PHASE C
PHASE C
1,2,3
PWM OUT
SYNC IN
100
PWM GND
ERROR AMP OUT
ERROR AMP IN
CURRENT
MONITOR OUT
-
+
100
ERROR
AMPLIFIER
-
+
IS+
10
CURRENT
AMP
Rsense
VBUS–
11,12,13
35
90.9
FIGURE 1. PWR-82520 BLOCK DIAGRAM
©
1994, 1999 Data Device Corporation
TABLE 1. ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
Bus Voltage
+15V Supply
-15V Supply
Continuous Output Current
Peak Output Current
Command input +
Command input -
Logic inputs
Sync Input
SYMBOL
VBUS+
V
DD
V
EE
I
OC
I
PEAK
Command input+
Command input-
ENABLE
HA, HB, HC
SYNC
VALUE
100
+17.5
-17.5
10
15
±15
±15
7.0
±15.0
UNITS
VDC
VDC
VDC
A
A
VDC
VDC
VDC
VDC
TABLE 2. PWR-82520 SPECIFICATIONS
(Unless otherwise specified, VBUS = 28 VDC, V
DD
= +15V, V
EE
= -15V, T
C
= 25°C)
PARAMETERS
OUTPUT
Output Current Continuous
Output Current Pulsed
Current Limit
Current Offset
Output On-Resistance
Output On-Resistance
Output Conductor Resistance
Load Inductance
COMMAND IN+/-
Differential Input
COMMAND OUT
Internal Voltage Clamp
CURRENT COMMAND
Transconductance ratio
Non-Linearity
CURRENT MONITOR AMP
Current Monitor Gain
Current Monitor Offset
Output Current
Output Resistance
VBUS+ SUPPLY
Nominal Operating Voltage
VBUS- To PWM GND
Voltage differential
+15 VDC
Voltage
Current
-15 VDC
Voltage
Current
SYNC (Note 2)
Voltage
Pulse Width
Sync range as % of free-run
frequency
SYMBOL
I
OC
(note 1)
I
OP
I
CL
I
OFFSET
R
ON
(note 2, 3)
R
ON
(note 2, 3)
R
C
L
MIN
V
DIF
V
CLMP
G
See FIGURE 9
TEST CONDITIONS
MIN
VALUE
TYP
MAX
UNITS
10
14
15.4
+0.3
0.040
0.055
A
A
A
A
Ω
Ω
Ω
µH
VDC
VDC
A/V
%
V/A
VDC
mA
Ω
VDC
VDC
VDC
mA
VDC
mA
V
ns
%
V
DF
= 0V
+25°C
+85°C
+85°C
12.0
-0.3
14.0
-
note 3
100
-10
-11.5
0.95
-3.0
0.97
-0.1
-10
1.0
+10
+11.5
1.05
+3.0
1.03
0.1
10
100
+70
0.250
+14.25
+15.0
100
-15.0
80
+15.75
150
-14.25
150
V
DF
= 0V
R
OUT
V
NOM
V
GNDDIF
V
S
+
I+
V
S
-
I-
1.0
0
+18
+28
-15.75
See FIGURE 7
±7.5
130
0
+20
Note:
1)
I
OC
is average current as measured in motor winding
2) Guaranteed by design, not tested.
3) The maximum output conductor resistance and on-resistance of FETs at +85°C are:
ΦA
U
= 0.20Ω,
ΦA
L
= 0.16Ω,
ΦB
U
= 0.08Ω,
ΦB
L
= 0.08Ω,
ΦC
U
= 0.08Ω,
ΦC
L
= 0.20Ω
2
TABLE 2. PWR-82520 SPECIFICATIONS (CONTINUED)
(Unless otherwise specified, VBUS = 28 VDC, V
DD
= +15V, V
EE
= -15V, T
C
= 25°C)
VALUE
PARAMETERS
PWM IN
+Peak
-Peak
Frequency
Non -linearity
Duty Cycle
PWM OUT
Free Run Frequency
HALL POWER SUPPLY
Max Current Draw
HALL SIGNALS
Logic 1
Logic 0
ENABLE INPUT
Enabled
Disabled
ISOLATION
CASE to PIN
SWITCHING CHARACTERISTICS
Upper drive
Turn-on Rise Time
Turn-off Fall Time
Lower drive
Turn-on Rise Time
Turn-off Fall Time
Diode Forward Voltage Drop
PROPAGATION DELAY
Td (on)
Td (off)
THERMAL
Thermal Resistance
Junction - Case
Case - Air
Junction Temperature
Case Operating Temperature
Case Storage Temperature
WEIGHT
From
to
From
to
I
MDRW
HA, HB,
HC
ENABLE
3.5
—
—
3.5
500 VDC HIPOT
10
SYMBOL
TEST CONDITIONS
MIN
9.8
-10.2
10
-2
49
45
TYP
10.0
-10.0
MAX
10.2
-9.8
60
+2
51
55
50
—
0.7
0.7
—
UNITS
V
P
+
V
P
-
f
LIN
D CYCLE
50
50
V
V
KHz
%
%
KHz
mA
VDC
VDC
VDC
MΩ
tr
tf
tr
tf
V
F
125
200
I
p
= 4 A
200
200
1.25
40
20
ns
ns
ns
ns
V
µs
µs
I
D
= 1A
Ip = 4A
0.7V on ENABLE
10% of VOUT
3.5V on ENABLE
90% of VOUT
θ
J-C
θ
C-A
T
J
T
C
T
CS
-55
-65
6
10
+175
+125
+150
1.7(48)
°C/W
°C/W
°C
°C
°C
oz(gr)
INTRODUCTION
The PWR-82520 is high performance current control (torque
loop) hybrid which use complementary four quadrant switching
topology (See BASIC OPERATION) to provide linearity through
zero current. The high Pulse Width Modulation (PWM) switching
frequency makes it suitable for even low inductance motors. The
PWR-82520 hybrid can accept single-ended or differential mode
command signals. The current gain can be easily programmed
to match the end user system requirements. With the compen-
sation network externally wired, the hybrid can provide optimum
control of a wide range of loads.
The PWR-82520 uses unique current sense technology and a
non-inductive hybrid sense resistor which yields a highly linear
current output over the wide military temperature range (see
FIGURE 9). The output current non-linearity is better than 3%
3
over the operating temperature range and the total error due to
all the factors such as offset, initial component accuracies etc. is
maintained well below 5% of the rated output current.
The Hall sensor interface for current commutation has built-in
decoder logic that separates illegal codes and ensures that there
is no cross conduction. The hybrid also has a +15V supply out-
put for powering the Hall sensors. The Hall sensor inputs are
internally pulled up to +5V and they can be driven from open-col-
lector outputs.
The PWM frequency can be programmed externally by adding a
capacitor from PWM OUT to PWM GND. In addition, multiple
PWR-82520’s can be synchronized by using one device as a
master and connecting its PWM OUT pin to the PWM IN of all
the other slave devices in a system or by applying a SYNC pulse
to pin 22.
The ENABLE input signal provides quick start and shutdown of
the output power switches. In addition, built-in power sequence
fault protection turns off the output in case of low power supply
voltages.
The hybrid features dual current limiting functions. The input
command amplifier output is limited to 10.8V thus limiting the
current under normal operation. In addition, there is a built in
over current limit which trips at 14 Amps, protecting the hybrid as
well as the load.
V
BUS
ON PHASE A
UPPER
I
PHASE A
+
PHASE B
-
PHASE B OFF
UPPER
BASIC OPERATION
The PW-82520 utilizes a complimentary four-quadrant drive
technique to control current in the load. The complimentary
drive has the following advantages over the standard drive:
1. Maximum holding torque and position accuracy
2. Linear current control through zero
3. No deadband at zero
The complementary drive design uses a 50% PWM duty cycle
for a zero command signal. For a zero input command, a pair of
MOSFETs are turned on in the drive, Phase A upper & Phase B
lower as shown in FIGURE 2A, to supply current into the load for
the first half of the PWM cycle. This is the same mode of oper-
ation for the standard four-quadrant drive as shown in FIGURE
3A/B. During the second half of the PWM cycle, a second pair
of transistors are turned on, Phase A lower & Phase B upper as
shown in FIGURE 2B, for the flyback current and to provide load
current in the opposite direction.
This is normally the dead time for standard four-quadrant drive
as shown in FIGURE 3B. The result is current flowing in both
directions in the motor for each PWM cycle. The advantage this
has over standard four-quadrant drive is that at 50% duty cycle,
which corresponds to zero average current in the motor, holding
torque is provided. The motor current at 50% duty cycle is sim-
ply the magnetizing current of the motor winding.
Using the complimentary four-quadrant technique allows the
motor direction to be defined by the duty cycle. Relative to a
given switch pair i.e., Phase A upper and Phase B lower, a duty
cycle greater than 50% will result in a clockwise rotation where-
as a duty cycle less than 50% will result in a counter clockwise
rotation. Therefore, with the use of average current mode con-
trol, direction can be controlled without the use of a direction bit
and the current can be controlled through zero in a very precise
and linear fashion.
The PW-82520 contains all the circuitry required to close an
average current mode control loop around a complimentary four-
quadrant drive. The PWR-82520 use of average current mode
control simplifies the control loop by eliminating the need for
slope compensation and eliminating the pole created by the
motor inductance. These two effects are normally associated
with 50% duty cycle limitations when implementing standard
peak current mode control.
OFF
PHASE A
LOWER
PHASE C
PHASE B
LOWER
ON
Rsense
FIGURE 2A. COMPLEMENTARY FOUR-QUANDRANT
DRIVE FIRST HALF OF PWM CYCLE
V
BUS
OFF PHASE A
UPPER
PHASE A
_
I
PHASE B
+
PHASE B
UPPER
ON
ON
PHASE A
LOWER
PHASE C
PHASE B
LOWER
OFF
Rsense
FIGURE 2B. COMPLEMENTARY FOUR-QUADRANT DRIVE
SECOND HALF OF PWM CYCLE
4
V
BUS
FUNCTIONAL AND
PIN
DESCRIPTIONS:
ON PHASE A
UPPER
I
PHASE A
+
PHASE B
-
PHASE B OFF
UPPER
COMMAND IN+, COMMAND IN-
(Pins 30 & 31)
The command amplifier has a differential input that operates
from a ±10 V analog current command. The differential input
voltage may vary between ±10 VDC, maximum, corresponding
to ±maximum voltage or current for the output. Either input
(COMMAND IN + or COMMAND IN-) may be referenced to the
command ground (Pin 29) and the other input varied from ±10
VDC to obtain full output. The COMMAND OUT signal is inter-
nally limited to approximately ±11.5 VDC; that is, inputs above or
below ±11.5 VDC will be clamped to ±11.5 VDC. The input
impedance of the Command Amplifier is 10K Ohms.
The PWR-82520 can be used either as a current or voltage
mode controller. When the PWR-82520 is used as a torque
amplifier (current mode) as shown in FIGURE 13, the transfer
function of the command amplifier is 1.0 A/V. The input com-
mand signal is processed through the command buffer. The out-
put of the buffer (COMMAND OUT) is summed with the current
monitor output into the error amplifier. When external compen-
sation is used on the error amp, as shown in FIGURE 6A, the
response time can be adjusted to meet the application.
When used in the voltage mode the Voltage Command uses the
same differential input terminals to control the voltage applied to
the motor (see FIGURE 12). The error amp directly varies the
PWM duty cycle of the voltage applied to the motor phase. The
transfer function in the voltage mode is 4.7% /V ±5% variation of
the PWM duty cycle vs. input command. The duty cycle range of
the output voltage is limited to approximately 5-95% in both cur-
rent and voltage modes.
OFF
PHASE A
LOWER
PHASE C
PHASE B
LOWER
ON
Rsense
FIGURE 3A. STANDARD FOUR QUANDRANT DRIVE FIRST
HALF OF PWM CYCLE
TRANSCONDUCTANCE RATIO AND OFFSET
V
BUS
OFF PHASE A
UPPER
PHASE A
_
PHASE B
+
PHASE B OFF
UPPER
When the PWR-82520 is used in the Current Mode, the com-
mand inputs (COMMAND IN+ and COMMAND IN-) are designed
such that ±10 VDC on either input, with the other input connect-
ed to Ground, will result in ±10 DC Average Amperes of current
into the load. The DC current transfer ratio accuracy is ±5% of
the rated output current. The initial output DC current offset with
both COMMAND IN+ and COMMAND IN- tied to the Ground will
be less than 100 mA when measured using a load of 0.5 mH and
1.0 Ohms at room ambient with standard current loop compen-
sation (see FIGURE 6A). The winding phase current error shall
be within the cumulative limits of the transconductance ratio
error and the offset error.
I
Flyback
OFF
PHASE A
LOWER
PHASE C
PHASE B
LOWER
OFF
HALL A,B,C SIGNALS
(Pins 37, 38 and 39)
These are logic signals from the motor Rotor Position Sensors
(HA, HB, HC). They use a phasing convention referred to as 120
degree spacing; that is, the output of HA is in phase with motor
back EMF voltage VAB, HB is in phase VBC, and HC is in phase
with VCA. Logic “1” (or HIGH) is defined by an input greater than
3.5 VDC or an open circuit to the controller; Logic “0” (or LOW)
is defined as any Hall voltage input less than 0.7 VDC. Internal
to the PWR-82520 are 5K pull-up resistors tied to +5 VDC on
each Hall input.
The PWR-82520 will operate with Hall phasing of 60° or 120°
electrical spacing. If 60° commutation is used, then the output of
5
Rsense
FIGURE 3B. STANDARD 4 QUANDRANT DRIVE SECOND
HALF OF PWM CYCLE
FPGA/CPLD
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