STB3NK60ZT4, STD3NK60Z-1, STD3NK60ZT4
STP3NK60Z, STP3NK60ZFP
Datasheet
N-channel 600 V, 3.2 Ω typ., 2.4 A SuperMESH™ Power MOSFETs in
D²PAK, IPAK, DPAK, TO-220 and TO-220FP packages
TAB
TAB
3
Features
1
2
1
D
2
PAK
TAB
3
TAB
2 3
1
Order codes
STB3NK60ZT4
STD3NK60Z-1
STD3NK60ZT4
V
DS
R
DS(on)
max.
I
D
Package
D
2
PAK
IPAK
IPAK
DPAK
3
1
2
600 V
3.6 Ω
2.4 A
DPAK
TO-220
TO-220FP
1
TO-220
2
3
STP3NK60Z
STP3NK60ZFP
TO-220FP
D(2, TAB)
G(1)
•
•
•
•
•
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitance
Zener-protected
Applications
S(3)
AM01475V1
•
Switching applications
Description
Product status link
STB3NK60ZT4
STD3NK60Z-1
STD3NK60ZT4
STP3NK60Z
STP3NK60ZFP
These high-voltage devices are Zener-protected N-channel Power MOSFETs
developed using the SuperMESH™ technology by STMicroelectronics, an
optimization of the well-established PowerMESH™. In addition to a significant
reduction in on-resistance, these devices are designed to ensure a high level of dv/dt
capability for the most demanding applications.
DS2912
-
Rev 6
-
August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STB3NK60ZT4,STD3NK60Z-1,STD3NK60ZT4,STP3NK60Z,STP3NK60ZFP
Electrical ratings
1
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
V
DS
V
GS
I
D
I
D
I
DM
(2)
P
TOT
ESD
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Gate-source human body model
(R = 1.5 kΩ, C = 100 pF)
Insulation withstand voltage (RMS)
V
ISO
dv/dt
(3)
T
j
T
stg
from all three leads to external heat-sink
(t = 1 s, T
C
= 25 °C)
Peak diode recovery voltage slope
Operating junction temperature range
Storage temperature range
2.5
4.5
-55 to 150
kV
V/ns
°C
2.4
1.51
9.6
45
Value
D
2
PAK, TO-220
TO-220FP
600
±30
2.4
(1)
1.51
(1)
9.6
(1)
20
2.1
2.4
1.51
9.6
45
DPAK, IPAK
Unit
V
V
A
A
A
W
kV
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. I
SD
≤ 2.4 A, di/dt ≤ 200 A/μs, V
DSpeak
≤ V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
Table 2.
Thermal data
Symbol
R
thj-case
R
thj-amb
R
thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-
ambient
Thermal resistance junction-pcb
35
Value
D
2
PAK
TO-220
2.78
62.5
50
TO-220FP
6.25
DPAK
2.78
100
IPAK
Unit
°C/W
°C/W
°C/W
1. When mounted on an 1-inch² FR-4, 2oz Cu board.
Table 3.
Avalanche characteristics
Symbol
I
AR
Parameter
Avalanche current, repetitive or not-
repetitive
(pulse width limited by T
j
Max)
Single pulse avalanche energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
2.4
Unit
A
E
AS
150
mJ
DS2912
-
Rev 6
page 2/34
STB3NK60ZT4,STD3NK60Z-1,STD3NK60ZT4,STP3NK60Z,STP3NK60ZFP
Electrical characteristics
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 4.
On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source breakdown
voltage
Zero gate voltage drain
current
Gate body leakage
current
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 1 mA, V
GS
= 0 V
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V, T
C
= 125 °C
(1)
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 50 µA
V
GS
= 10 V, I
D
= 1.2 A
3
3.75
3.2
Min.
600
1
50
±10
4.5
3.6
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
1. Defined by design, not subject to production test.
Table 5.
Dynamic
Symbol
C
iss
C
oss
C
rss
C
oss eq.
(1)
Q
g
Q
gs
Q
gd
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 0 to 480 V, V
GS
= 0 V
V
DD
= 480 V, I
D
= 2.4 A, V
GS
= 0 to 10 V
(see
Figure 16. Test circuit for gate charge
behavior)
-
V
DS
= 25 V, f = 1 MHz, V
GS
= 0 V
-
Test conditions
Min.
Typ.
311
43
8
26
11.8
-
2.6
6.4
-
-
-
nC
pF
-
pF
Max.
Unit
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0
to 80% V
DSS
.
Table 6.
Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 300 V, I
D
= 1.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 15. Test circuit for resistive load
switching times
and
Figure 20. Switching
time waveform)
-
Min.
Typ.
9
14
19
14
-
ns
Max.
Unit
DS2912
-
Rev 6
page 3/34
STB3NK60ZT4,STD3NK60Z-1,STD3NK60ZT4,STP3NK60Z,STP3NK60ZFP
Electrical characteristics
Table 7.
Source drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t
rr
Q
rr
I
RRM
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 2.4 A, V
GS
= 0 V
I
SD
= 2.4 A, di/dt = 100 A/µs
V
DD
= 48 V, T
j
= 150°C (see
Figure 17. Test
circuit for inductive load switching and
diode recovery times)
-
-
Test conditions
Min.
Typ.
Max.
2.4
9.6
1.6
306
948
6.2
A
Unit
-
V
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
Table 8.
Gate-source Zener diode
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown
voltage
Test conditions
I
GS
= ±1 mA, I
D
= 0 A
Min.
±30
Typ.
-
Max.
-
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for
additional external componentry.
DS2912
-
Rev 6
page 4/34
STB3NK60ZT4,STD3NK60Z-1,STD3NK60ZT4,STP3NK60Z,STP3NK60ZFP
Electrical characteristics curves
2.1
Electrical characteristics curves
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Safe operating area for TO-220FP
Figure 4.
Thermal impedance for TO-220FP
K
GC20940
10
-1
10
-2
10
-3
10
-4
10
-3
10
-2
10
-1
10
0
t
p
(s)
Figure 5.
Output characterisics
Figure 6.
Transfer characteristics
DS2912
-
Rev 6
page 5/34
Analogue and Mixed Signal
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