EEWORLDEEWORLDEEWORLD

Part Number

Search

2708DLQR

Description
OTP ROM, 1KX8, MOS, CDIP24,
Categorystorage    storage   
File Size222KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

2708DLQR Overview

OTP ROM, 1KX8, MOS, CDIP24,

2708DLQR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
package instructionDIP, DIP24,.6
Reach Compliance Codecompli
ECCN codeEAR99
Maximum access time450 ns
JESD-30 codeR-XDIP-T24
JESD-609 codee0
memory density8192 bi
Memory IC TypeOTP ROM
memory width8
Number of terminals24
word count1024 words
character code1000
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX8
Output characteristics3-STATE
Package body materialCERAMIC
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.6
Package shapeRECTANGULAR
Package formIN-LINE
surface mountNO
technologyMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
3225 passive crystal oscillator pin definition
[color=rgb(85, 85, 85)][font=微软雅黑, Tahoma,]Bottom view of passive crystal oscillator[/font][/color] [color=rgb(85, 85, 85)][font=微软雅黑, Tahoma,]As shown below: The pad pointed by the arrow in the botto...
扬兴科技 Industrial Control Electronics
The DIY smart home control part is about to be released, if you are interested, please sign up
Today I discussed with Xiaoyang and other main designers, and asked them to help check it again to ensure the smooth progress of our first project.This is the overall solution for smart home:Smart Hom...
soso DIY/Open Source Hardware
UltraEdit's SystemVerilog keyword settings sharing
The SystemVerilog part is at the end of the file (starting with /L15). Everyone has different idiomatic languages. If you only need to add the SystemVerilog part and keep other settings, just copy thi...
eeleader FPGA/CPLD
Problems encountered in PCI Express design
Use Spartan-6 to make a simple PCIE communication board. When generating the PCIE IP core, open up BAR0 as 128 bytes of IO space, and then directly use the generated reference design to generate the b...
eeleader FPGA/CPLD
The process of 51 single-chip microcomputer executing instructions [Original]
In order to deepen the understanding of 51 single-chip microcomputer instructions for beginners, the process of instruction execution is now described in detail here, hoping to inspire you! The proces...
fdsifhdui 51mcu
Design of dedicated active filter for surface electromyography signal pickup
Electronic Information Network IntroductionMyoelectric signals are the temporal and spatial superposition of motor unit action potentials (MUAPs) in muscles, while surface electromyographic signals ar...
fighting Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1672  2015  1321  322  1942  34  41  27  7  40 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号