Data Sheet No. PD94146
IRU3027
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC
WITH TRIPLE LDO CONTROLLER
FEATURES
DESCRIPTION
Designed to meet VRM 9.0 specification for next
generation microprocessors
On-Board 5-Bit DAC programs the output voltage
from 1.075V to 1.850V in 25mV steps
Linear Regulator Controller On-Board for 1.8V
Provides single chip solution for Vcore, GTL+,
AGP bus, and 1.8V
Automatic Voltage Selection for AGP Slot V
DDQ
Supply
Linear Regulator Controller On-Board for 1.5V
GTL+ Supply
Loss-less Short Circuit Protection for all Outputs
Synchronous operation allows maximum effi-
ciency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole driver for direct driving of
the external power MOSFET
Power Good function monitors all outputs
Over-Voltage Protection Circuitry protects the
switcher output and generates a fault output
The IRU3027 controller IC is specifically designed to meet
VRM 9.0 specification for next generation microproces-
sor applications requiring multiple on-board regulators.
The IRU3027 provides a single chip controller IC for the
Vcore, three LDO controllers, one with an automatic se-
lect pin that connects to the Type Detect pin of the AGP
slot for the AGP V
DDQ
supply, one for GTL+ and the other
for the 1.8V chip set regulator as required for the next
generation PC applications. The IRU3027 is designed to
use either bipolar transistors for V
OUT
3(1.5V) and
V
OUT
4(1.8V). No external resistor divider is necessary
for any of the regulators. The switching regulator fea-
tures a patented topology that in combination with a few
external components as shown in the typical applica-
tion circuit, will provide well in excess of 20A of output
current for an on-board DC-DC converter while automati-
cally providing the right output voltage via the 5-bit inter-
nal DAC. The IRU3027 also features loss-less current
sensing for both switchers by using the R
DS(ON)
of the
high side power MOSFET as the sensing resistor, an
output under-voltage shutdown that detects short circuit
condition for the linear outputs and latches the system
off, and a Power Good window comparator that switches
its open collector output low when any one of the out-
puts is outside of a pre-programmed window.
APPLICATIONS
Total power solution for next generation Intel
processor application
AMD K7 Low Cost Solution
TYPICAL APPLICATION
5V
3.3V
LINEAR
CONTROL
SWITCHER
CONTROL
V
OUT
1
V
OUT
2
IRU3027
LINEAR
CONTROL
V
OUT
3
LINEAR
CONTROL
V
OUT
4
Figure 1 - Typical application of IRU3027.
PACKAGE ORDER INFORMATION
T
A
(8C)
0 To 70
Rev. 1.5
07/17/02
DEVICE
IRU3027CW
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PACKAGE
28-Pin Plastic SOIC WB
1
IRU3027
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage ....................................................
V12 Supply Voltage ..................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
20V
-65 To 150°C
0 To 125°C
PACKAGE INFORMATION
28 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
Drive2
1
Fix
2
VID4
3
VID3
4
VID2
5
VID1
6
VID0
7
PGood
8
SD
9
V
SEN
2
10
Select
11
SS
12
Fault / Rt
13
V
SEN
4
14
28
V12
27
UGate
26
Phase
25
LGate
24
PGnd
23
OCSet
22
V
SEN
1
21
Fb
20
V5
19
V
SEN
3
18
Drive3
17
Gnd
16
NC
15
Drive4
u
JA
=808C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70°C. Typical values refer
to T
A
=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Supply UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Supply Current
Operating Supply Current
SYM
TEST CONDITION
Supply Ramping Up
Supply Ramping Up
MIN
TYP
10
0.6
4.4
0.3
6
30
MAX
UNITS
V
V
V
V
mA
V12
V5
Switching Controllers; Vcore (V
SEN
1) and AGP (V
SEN
2)
VID Section (Vcore only)
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
V
SEN
2 Voltage
Select <0.8V
Select >2V
0.99Vs
Vs
0.1
0.5
1.01Vs
0.8
2
27
1.5
3.3
V
%
%
V
V
KV
V
2
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Rev. 1.5
07/17/02
IRU3027
PARAMETER
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Outout
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Output Drivers Section
Rise Time
Fall Time
Dead Band Time Between
High Side and Synch Drive
(Vcore Switcher Only)
Oscillator Section (Internal)
Osc Frequency
1.8V Regulator (V
SEN
4)
V
SEN
Voltage
V
SEN
Voltage
Input Bias Current
Output Drive Current
1.5V Regulator (V
SEN
3)
V
SEN
Voltage
V
SEN
Voltage
Input Bias Current
Output Drive Current
Power Good Section
V
SEN
1 UV Lower Trip Point
V
SEN
1 UV Upper Trip Point
V
SEN
1 UV Hysterises
V
SEN
1 HV Upper Trip Point
V
SEN
1 HV Lower Trip Point
V
SEN
1 HV Hysterises
V
SEN
2 Trip Point
V
SEN
3 Trip Point
V
SEN
4 Trip Point
Power Good Output LO
Power Good Output HI
Fault (Overvoltage) Section
Core OV Upper Trip Point
Core OV Lower Trip Point
Fault Output HI
Soft-Start Section
Pull-Up Resistor to 5V
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
2
+2
100
200
-5
Css=0.1mF
C
L
=3000pF
C
L
=3000pF
C
L
=3000pF
10
70
70
200
+5
mA
mV
ns
mA
mV
%
ns
ns
ns
-2
V
DIFF
=10mV
Rt=Open
V
O
4
T
A
=258C, Drive4=V
SEN
4
217
1.800
1.800
2
50
KHz
V
V
mA
mA
V
V
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
V
O
3
T
A
=258C, Drive3=V
SEN
3
1.500
1.500
2
50
V
SEN
1 Ramping Down
V
SEN
1 Ramping Up
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
Select <0.8V
Select >2V
Fix=Gnd
Fix=Open
Fix=Gnd
Fix=Open
R
L
=3mA
R
L
=5K, Pull-Up to 5V
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
Io=3mA
OCSet=0V, Phase=5V
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
1.100
2.560
0.920
1.320
0.920
1.140
0.4
4.8
1.17Vs
1.15Vs
10
20
Note 1:
Vs refers to the set point voltage given in Table 1.
Rev. 1.5
07/17/02
www.irf.com
3
IRU3027
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
Table 1 - Set point voltage vs. VID codes.
PIN DESCRIPTIONS
PIN#
1
2
PIN SYMBOL
Drive2
Fix
PIN DESCRIPTION
This pin controls the gate of an external MOSFET for the AGP linear regulator.
Leaving this pin open provides fixed output voltages of the 1.5V and 1.8V for the #3 and
#4 linear regulators. When this pin is grounded the reference to the linear regulators are
set to 1.26V and therefore the output of the regulators can be programmed to any volt-
ages above the 1.26V using: V
OUT
= 1.26
3
(1 + R
TOP
/R
BOT
)
Where:
R
TOP
=Top resistor connected from the output to the V
SENSE
pin
R
BOT
=Bottom resistor connected from the V
SENSE
pin to ground.
This pin selects a range of output voltages for the DAC. When in the LOW state the
range is 1.3V to 2.05V and when it switches to HI state the range is 2V to 3.5V. This pin
is TTL compatible that realizes a logic “1” as either HI or Open. When left open, this pin
is pulled up internally by a 27KV resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KV resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KV resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under-voltage trip point. It also switches low when V
SEN
1 pin is more than
10% above the DAC voltage setting.
3
VID4
4
VID3
5
VID2
6
VID1
7
VID0
8
PGood
4
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Rev. 1.5
07/17/02
IRU3027
PIN#
9
PIN SYMBOL
SD
PIN DESCRIPTION
This pin provides shutdown for all the regulators. A TTL compatible, logic level high applied
to this pin disables all the outputs and discharges the soft-start capacitor. The SD signal
turns off the synchronous allowing the body diode to conduct and discharge the output
capacitor.
This pin provides the feedback for the AGP linear regulator. The Select pin when con-
nected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for
the AGP V
DDQ
.
This pin provides automatic voltage selection for the AGP switching regulator. When it is
pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V.
This pin provides the soft-start for all the regulators. An internal current source charges an
external capacitor that is connected from this pin to ground which ramps up the outputs of
the regulators, preventing the outputs from overshooting as well as limiting the input cur-
rent. The second function of the Soft-Start cap is to provide long off time (HICCUP) for the
synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the over-voltage protection circuitry or it
can be used to program the frequency using an external resistor . When used as a fault
detector, if any of the switcher outputs exceed the OVP trip point, the Fault pin switches
to 12V and the soft-start cap is discharged. If the Fault pin is to be connected to any
external circuitry, it needs to be buffered.
This pin provides the feedback for the linear regulator that its output drive is Drive4.
This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator.
This pin has no connection.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Drive3.
5V supply voltage. A high frequency capacitor (0.1 to 1mF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to V
OUT
1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from V
OUT
1 to Fb1 must be less than 1000V.
This pin is internally connected to the under-voltage and over-voltage comparators sens-
ing the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the current sense threshold depending on the R of the power MOSFET. An
DS
external capacitor is placed in parallel with the programming resistor to provide high fre-
quency noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-
cally 1mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1mF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for the noise free
operation.
10
V
SEN
2
11
12
Select
SS
13
Fault / Rt
14
15
16
17
18
19
20
21
V
SEN
4
Drive4
NC
Gnd
Drive3
V
SEN
3
V5
Fb
22
23
V
SEN
1
OCSet
24
PGnd
25
26
27
28
LGate
Phase
UGate
V12
Rev. 1.5
07/17/02
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