IP113A LF
Preliminary Data Sheet
10 /100Base-Tx/Fx Media Converter
Features
A 10/100BASE-TX/ 100BASE-FX converter
Built in a 10/100BASE-TX transceiver
Built in a PHY for 100BASE-FX
Built in a 2-port switch
– Pass all packets without address and
CRC check (optional)
– Supports modified cut-through frame
forwarding for low latency
– Supports pure converter mode data
forwarding for extreme low latency
– Supports flow control for full and half
duplex operation
– Bandwidth control
– Forward 1600 bytes packet for
management
– Optional forward fragments
Built in 128Kb RAM for data buffer
Supports auto MDI-MDIX function
Supports link fault pass through function
Supports far end fault function
LED display for link/activity, full/half, 10/100
Built in a watchdog timer to monitor internal
switch error
Supports EEPROM Configuration
0.25u CMOS technology
Single 2.5V power supply
48-pin LQFP package
Support Lead Free package (Please refer to
the Order Information)
General Description
IP113A LF can be a 10/100BASE-TX to
100BASE-FX converter. It consists of a 2-port
switch controller, a fast Ethernet transceiver and a
PHY for 100BASE-FX. The transceivers in IP113A
LF are designed in DSP approach with advance
0.25-um technology; this results in high noise
immunity and robust performance.
IP113A LF not only supports store and forward
mode, it also supports modified cut through mode
and pure converter mode for low latency data
forwarding. IP113A LF can transmit packet(s) up
to 1600 bytes to meet requirement of extra long
packets.
IP113A LF supports IEEE802.3x, collision base
backpressure, and various LED functions, etc.
These functions can be configured to fit the
different requirements by feeding operation
parameters via EEPROM interface or pull
up/down resistors on specified pins.
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Copyright © 2004, IC Plus Corp.
April 9, 2007
IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
Block Diagram
SSRAM
PLL/ Clock
Generator
RXIP
RXIM
TXOP
TXOM
10/100M TX
PHY
MII
Two port switch
MII
100M FX
FXSD
FXRDP
FXRDM
FXTDP
FXTDM
SCL
SDA
EEPROM
I/F
Forward Mode
Control
LED
I/F
LED
Revision History
Revision #
IP113A LF-DS-R01
IP113A LF-DS-R02
IP113A LF-DS-R03
IP113A LF-DS-R04
IP113A LF-DS-R05
IP113A LF-DS-R06
Change Description
Initial release.
Remove
Operation Junction Temperature.
TP port should be linked at 100M full duplex when working at this mode.
Add the order information for lead free package.
Revise the diagram.
TP_FORCE (Pin24) &X_EN(Pin29)
It is an input pin during reset period. The default value is latched at the end of reset.
IP113A LF-DS-R07 Remove internal pull-high resistance & pull-low resistance on page 5.
Modify the IPL : pull-low and IPH : pull-high
IP113A LF-DS-R08
Add Power Pin description on Page10
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Copyright © 2004, IC Plus Corp.
April 9, 2007
IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
1. PIN Description
Type
I
O
IPL
IPH
Description
Input pin
Output pin
Input pin with internal pull-low resistor.
Input pin with internal pull-high resistor.
Pin no.
Transceiver
5, 6
8, 9
2
Label
Type
Description
RXIP, RXIM
TXOP, TXOM
BGRES
I
O
O
TP receive
TP transmit
Band gap resistor
It is connected to GND through a 6.19k (1%) resistor in
application circuit.
100Base-FX signal detect
Fiber signal detect. It is an input signal from fiber MAU.
Fiber signal detect is active if the voltage on FXSD is higher
than the threshold voltage, which is 1.35v
±5%
when VCC
is equal to 2.5v.
Fiber receiver data pair
Common-mode voltage of FXRDP and FXRDM are
suggested to near 0.5x AVCC.
When voltage peak-to-peak>0.1V,FXRX could be
workable.
Fiber transmitter data pair
FXTX with the external 100Ω resistor.
Common-mode voltage of FXTDP and FXTDM are
suggested to near 0.5x AVCC.
Swing of Voltage
≧ 0.8V.
18
FXSD
I
13, 14
FXRDP, FXRDM
I
16, 17
FXTDP, FXTDM
O
5/22
Copyright © 2004, IC Plus Corp.
April 9, 2007
IP113A LF-DS-R08
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