5AGXMA7G4F31I5 datasheet, PDF - EEWORLD Datasheet

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5AGXMA7G4F31I5: DescriptionField Programmable Gate Array, 622MHz, PBGA896, FBGA-896; CategoryProgrammable logic devices Programmable logic; File Size2MB，176 Pages; ManufacturerAltera (Intel)

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5AGXMA7G4F31I5 Overview

Field Programmable Gate Array, 622MHz, PBGA896, FBGA-896

5AGXMA7G4F31I5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	BGA,
Contacts	896
Reach Compliance Code	compli
maximum clock frequency	622 MHz
JESD-30 code	S-PBGA-B896
JESD-609 code	e0
length	31 mm
Number of terminals	896
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Maximum seat height	2.7 mm
Maximum supply voltage	1.13 V
Minimum supply voltage	1.07 V
Nominal supply voltage	1.1 V
surface mount	YES
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	31 mm

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Arria V Device Datasheet

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AV-51002 | 2019.04.26

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Contents

1. Arria

V GX, GT, SX, and ST Device Datasheet....................................................................................................................... 4

1.1. Electrical Characteristics................................................................................................................................................ 4

1.1.1. Operating Conditions.........................................................................................................................................4

1.2. Switching Characteristics............................................................................................................................................. 24

1.2.1. Transceiver Performance Specifications.............................................................................................................. 25

1.2.2. Core Performance Specifications....................................................................................................................... 44

1.2.3. Periphery Performance.....................................................................................................................................49

1.2.4. HPS Specifications.......................................................................................................................................... 57

1.3. Configuration Specifications......................................................................................................................................... 74

1.3.1. POR Specifications.......................................................................................................................................... 74

1.3.2. FPGA JTAG Configuration Timing....................................................................................................................... 75

1.3.3. FPP Configuration Timing................................................................................................................................. 75

1.3.4. Active Serial (AS) Configuration Timing..............................................................................................................79

1.3.5. DCLK Frequency Specification in the AS Configuration Scheme..............................................................................80

1.3.6. Passive Serial (PS) Configuration Timing............................................................................................................ 81

1.3.7. Initialization................................................................................................................................................... 82

1.3.8. Configuration Files.......................................................................................................................................... 83

1.3.9. Minimum Configuration Time Estimation.............................................................................................................84

1.3.10. Remote System Upgrades.............................................................................................................................. 85

1.3.11. User Watchdog Internal Oscillator Frequency Specifications.................................................................................85

1.4. I/O Timing................................................................................................................................................................. 85

1.4.1. Programmable IOE Delay................................................................................................................................. 86

1.4.2. Programmable Output Buffer Delay................................................................................................................... 87

1.5. Glossary.................................................................................................................................................................... 87

1.6. Arria V GX, GT, SX, and ST Device Datasheet Revision History......................................................................................... 94

2. Arria V GZ Device Datasheet...............................................................................................................................................100

2.1. Electrical Characteristics............................................................................................................................................ 100

2.1.1. Operating Conditions .................................................................................................................................... 100

2.2. Switching Characteristics ...........................................................................................................................................119

2.2.1. Transceiver Performance Specifications ........................................................................................................... 119

2.2.2. Core Performance Specifications .....................................................................................................................133

Arria V Device Datasheet

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Contents

2.3.

2.4.

2.5.

2.6.

2.2.3. Periphery Performance .................................................................................................................................. 139

Configuration Specification ........................................................................................................................................ 151

2.3.1. POR Specifications ........................................................................................................................................151

2.3.2. JTAG Configuration Specifications ................................................................................................................... 151

2.3.3. Fast Passive Parallel (FPP) Configuration Timing ................................................................................................152

2.3.4. Active Serial Configuration Timing .................................................................................................................. 160

2.3.5. Passive Serial Configuration Timing .................................................................................................................163

2.3.6. Initialization ................................................................................................................................................ 165

2.3.7. Configuration Files ........................................................................................................................................165

2.3.8. Remote System Upgrades Circuitry Timing Specification .................................................................................... 167

2.3.9. User Watchdog Internal Oscillator Frequency Specification ................................................................................. 167

I/O Timing .............................................................................................................................................................. 167

2.4.1. Programmable IOE Delay .............................................................................................................................. 168

2.4.2. Programmable Output Buffer Delay .................................................................................................................169

Glossary ................................................................................................................................................................. 169

Arria V GZ Device Datasheet Revision History ............................................................................................................. 175

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Arria V Device Datasheet

AV-51002 | 2019.04.26

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1. Arria

V GX, GT, SX, and ST Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing

for Arria

V devices.

Arria V devices are offered in commercial and industrial grades. Commercial devices are offered in –C4 (fastest), –C5, and –

C6 speed grades. Industrial grade devices are offered in the –I3 and –I5 speed grades.

Related Information

Arria V Device Overview

Provides more information about the densities and packages of devices in the Arria V family.

1.1. Electrical Characteristics

The following sections describe the operating conditions and power consumption of Arria V devices.

1.1.1. Operating Conditions

Arria V devices are rated according to a set of defined parameters. To maintain the highest possible performance and

reliability of the Arria V devices, you must consider the operating requirements described in this section.

1.1.1.1. Absolute Maximum Ratings

This section defines the maximum operating conditions for Arria V devices. The values are based on experiments conducted

with the devices and theoretical modeling of breakdown and damage mechanisms.

The functional operation of the device is not implied for these conditions.

Caution:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device

operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current

specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel

assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in

writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing

orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2015

Registered

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