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CN6740-1200BG1936-AAP

Description
Microprocessor,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size171KB,2 Pages
ManufacturerMarvell
Websitehttp://www.marvell.com
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CN6740-1200BG1936-AAP Overview

Microprocessor,

CN6740-1200BG1936-AAP Parametric

Parameter NameAttribute value
MakerMarvell
package instruction,
Reach Compliance Codecompliant
Multi-Core MIPS64 Processors
R
OCTEON II CN67XX Multi-Core MIPS64 Processors
Product Brief
OVERVIEW
The OCTEON II CN67XX family of Multi-Core MIPS64 Processors targets high-performance, high-throughput,
service-rich applications in secure datacenter, mobile internet, and borderless enterprise applications. The family
includes six software and pin-compatible processors, with 8 to 16 cnMIPS64 v2 cores and full pin and software
compatibility with the OCTEON II CN68XX processor family which enables scaling up to a 32 cores using the same
hardware and software design. The CN67XX also offers over 60 application acceleration engines and the latest
standards-based connectivity including PCIe Gen2, XAUI, Double-speed XAUI, RXAUI, and Interlaken and provides
major compute performance, throughput, and services performance advantages over alternative solutions.
®
FEATURES
Up to 16 MIPS64 cores and 2x DDR3 controllers with
BENEFITS
Up to 24 GHz of total compute in a single chip
scalability in the same pinout to 32 cores and 4x
DDR3 controllers; SW compatible with OCTEON Plus
Latest, Highest-Bandwidth Serial I/O’s for Standard
Connectivity: XAUI/RXAUI, Interlaken, PCIe Gen 2
New LZS storage compression mode, compression/
decompression performance up to 20Gbps
Third generation Reg Ex Engine with revolutionary
Hyper Finite Automata (HFA) up to 15 Gbps
High-bandwith, low-latency I/O and coprocessor
networks
Hardware and software virtualization
Power Optimizer Technology with flexible, dynamic
control of device core power consumption
> 200Gbps DDR3 bandwidth
> 40 Gbps packet processing and security processing
with seamless connectivity to peripherals
Accelerates LZS to address additional storage
applications in addition to ZIP/PKZIP/GZIP support
Deterministic pattern matching performance,
independent of # of flows and rules, most compact
graph size
Linear performance scaling with full coprocessor
services at line rate
Ability to partition into multiple virtual SoCs
Flexible, dynamic power control to achieve best
performance/Watt
OCTEON
®
II CN67XX - Block Diagram
DMA
x20
Gen2
SERDES
FPA
Timers
10G or
4x 1G
Interlaken
Interlaken-LA
PCIe v2
2x 10G
10G or
4x 1G
10G or
4x 1G
Application
Acceleration
Manager
Compression
/Decomp
v3
RAID/
XOR
TCP
x4
x4
x4
x4
x4
If x4
If x8
Power
Optimizer
Crypto
Security
Packet
CN67XX
Crypto
Security
Packet
Secure Vault
MIPS64 r2
Integer Core
MIPS64 r2
8-16
cnMIPS II
Integer Core
cores
37K Icache
37K Icache
Misc I/0
HFA
(Pattern
Matching)
32K Dcache
Write Back Buffer
32K Dcache
Write Back Buffer
Boot/Flash
(NOR &
NAND), CF,
16 GPIO,
DUART, 2x
I2C,
USB 2.0
w/PHY,
1xRG/MII
PCIe v2
Packet
Input v2
Packet
Output v2
2x Hyper
Access
Memory
Controller v2
I/O
Network
Coproc
Network
4MB Shared
L2 Cache
2x 72b
2315 N. First Street
San Jose, CA 95131
T
408-943-7100
F
408-577-1992
E
sales@cavium.com
www.cavium.com

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Reach Compliance Code compliant compliant compliant compliant compliant
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