ISPLSI2032VE225LTN48I datasheet, PDF

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ISPLSI2032VE225LTN48I: Description3.3V In-System Programmable High Density SuperFASTâ¢ PLD; File Size247KB，15 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPLSI2032VE225LTN48I Overview

3.3V In-System Programmable High Density SuperFASTâ¢ PLD

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ispLSI 2032VE

3.3V In-System Programmable

High Density SuperFAST™ PLD

Functional Block Diagram

Features

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2032V Devices

• 3.3V LOW VOLTAGE 2032 ARCHITECTURE

— Interfaces With Standard 5V TTL Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 300 MHz Maximum Operating Frequency

—

= 3.0 ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability Using Boundary

Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

Output Routing Pool (ORP)

Input Bus

GLB

Logic

Array

D Q

0139Bisp/2000

Description

The ispLSI 2032VE is a High Density Programmable

Logic Device that can be used in both 3.3V and 5V

systems. The device contains 32 Registers, 32 Universal

I/O pins, two Dedicated Input Pins, three Dedicated

Clock Input Pins, one dedicated Global OE input pin and

a Global Routing Pool (GRP). The GRP provides

complete interconnectivity between all of these elements.

The ispLSI 2032VE features in-system programmability

through the Boundary Scan Test Access Port (TAP) and

is 100% IEEE 1149.1 Boundary Scan Testable. The

ispLSI 2032VE offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 2032VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

2032ve_11

Input Bus

D Q

Output Routing Pool (ORP)

Global Routing Pool

(GRP)

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