ISPLSI2192VE225LB144I datasheet, PDF

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ISPLSI2192VE225LB144I: Description3.3V In-System Programmable SuperFASTâ¢ High Density PLD; File Size154KB，15 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ISPLSI2192VE225LB144I Overview

3.3V In-System Programmable SuperFASTâ¢ High Density PLD

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ispLSI 2192VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

Functional Block Diagram

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

Output Routing Pool

Features

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 8000 PLD Gates

— 96 I/O Pins, Nine or Twelve Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Pinout Compatible with ispLSI 2096V and 2096VE

• 3.3V LOW VOLTAGE ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 225MHz Maximum Operating Frequency

—

= 4.0ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• LEAD-FREE PACKAGE OPTIONS

Output Routing Pool

E7 E6 E5 E4 E3 E2 E1 E0

Output Routing Pool

D Q

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

Logic

D Q

Global Routing Pool (GRP)

Array

D Q

GLB

D Q

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

Description

The ispLSI 2192VE is a High Density Programmable

Logic Device containing 192 Registers, nine or twelve

Dedicated Input pins, three Dedicated Clock Input pins,

two dedicated Global OE input pins and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2192VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2192VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

The basic unit of logic on the ispLSI 2192VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 2192VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2004

2192ve_10

CLK0

CLK1

CLK2

0139/2192VE

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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