PR E LI MIN ARY
LM3S2016 Microcontroller
DATA SHEE T
DS-LM3S2 016-1 97 2
Cop yr igh t
©
2 00 7 L umin ary Mi cro , In c.
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright
©
2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2
Preliminary
November 30, 2007
LM3S2016 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
20
25
25
26
27
27
28
28
30
30
31
31
34
34
34
35
35
35
35
35
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 20
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 33
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 39
Interrupts ............................................................................................................................ 41
JTAG Interface .................................................................................................................... 43
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
44
44
45
46
47
47
50
50
50
52
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 54
Functional Description ............................................................................................................... 54
Device Identification .................................................................................................................. 54
Reset Control ............................................................................................................................ 54
November 30, 2007
Preliminary
3
Table of Contents
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
57
57
59
59
60
61
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Internal Memory ............................................................................................................... 109
Block Diagram ........................................................................................................................ 109
Functional Description ............................................................................................................. 109
SRAM Memory ........................................................................................................................ 109
Flash Memory ......................................................................................................................... 110
Flash Memory Initialization and Configuration ........................................................................... 111
Flash Programming ................................................................................................................. 111
Nonvolatile Register Programming ........................................................................................... 112
Register Map .......................................................................................................................... 112
Flash Register Descriptions (Flash Control Offset) ..................................................................... 113
Flash Register Descriptions (System Control Offset) .................................................................. 120
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 133
Functional Description ............................................................................................................. 133
Data Control ........................................................................................................................... 134
Interrupt Control ...................................................................................................................... 135
Mode Control .......................................................................................................................... 136
Commit Control ....................................................................................................................... 136
Pad Control ............................................................................................................................. 136
Identification ........................................................................................................................... 136
Initialization and Configuration ................................................................................................. 136
Register Map .......................................................................................................................... 137
Register Descriptions .............................................................................................................. 139
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers ................................................................................................. 174
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
174
175
175
176
177
181
181
182
182
183
183
184
184
185
10
10.1
10.2
10.3
Watchdog Timer ............................................................................................................... 210
Block Diagram ........................................................................................................................ 210
Functional Description ............................................................................................................. 210
Initialization and Configuration ................................................................................................. 211
4
Preliminary
November 30, 2007
LM3S2016 Microcontroller
10.4
10.5
Register Map .......................................................................................................................... 211
Register Descriptions .............................................................................................................. 212
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) ................................................................................. 233
Block Diagram ........................................................................................................................ 234
Functional Description ............................................................................................................. 234
Sample Sequencers ................................................................................................................ 234
Module Control ........................................................................................................................ 235
Hardware Sample Averaging Circuit ......................................................................................... 236
Analog-to-Digital Converter ...................................................................................................... 236
Test Modes ............................................................................................................................. 236
Initialization and Configuration ................................................................................................. 236
Module Initialization ................................................................................................................. 236
Sample Sequencer Configuration ............................................................................................. 236
Register Map .......................................................................................................................... 237
Register Descriptions .............................................................................................................. 238
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 265
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
I
2
C Bus Functional Overview ....................................................................................................
Available Speed Modes ...........................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
Command Sequence Flow Charts ............................................................................................
266
266
266
267
268
268
269
269
270
270
270
271
272
306
306
307
307
307
308
315
316
317
343
343
344
346
347
347
348
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................ 306
14
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 343
November 30, 2007
Preliminary
5
stm32/stm8
京公网安备 11010802033920号
EEWORLD
