LM3S317-IQC50-B0 datasheet, PDF

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LM3S317-IQC50-B0: DescriptionMicrocontroller; File Size2MB，379 Pages; ManufacturerETC2

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P REL I MIN AR Y

LM3S317 Microcontroller

D A TA S H E E T

DS-LM3S31 7-02

Co pyrigh t © 200 7 Lumin ary Micro, In c.

LM3S317 Data Sheet

Table of Contents

Legal Disclaimers and Trademark Information.............................................................................. 2

Revision History ............................................................................................................................. 16

About This Document..................................................................................................................... 17

Audience........................................................................................................................................................... 17

About This Manual............................................................................................................................................ 17

Related Documents .......................................................................................................................................... 17

Documentation Conventions............................................................................................................................. 17

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.5

Architectural Overview ....................................................................................................... 20

Product Features ................................................................................................................................. 20

Target Applications .............................................................................................................................. 24

High-Level Block Diagram ................................................................................................................... 25

Functional Overview ............................................................................................................................ 26

ARM Cortex™-M3 ............................................................................................................................... 26

Motor Control Peripherals .................................................................................................................... 26

Analog Peripherals .............................................................................................................................. 27

Serial Communications Peripherals..................................................................................................... 27

System Peripherals.............................................................................................................................. 28

Memory Peripherals............................................................................................................................. 29

Additional Features .............................................................................................................................. 29

Hardware Details ................................................................................................................................. 30

System Block Diagram ........................................................................................................................ 31

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core........................................................................................ 32

Block Diagram ..................................................................................................................................... 33

Functional Description ......................................................................................................................... 33

Serial Wire and JTAG Debug .............................................................................................................. 33

Embedded Trace Macrocell (ETM) ...................................................................................................... 34

Trace Port Interface Unit (TPIU) .......................................................................................................... 34

ROM Table .......................................................................................................................................... 34

Memory Protection Unit (MPU) ............................................................................................................ 34

Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 34

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ........................................................................................................................ 40

Interrupts ............................................................................................................................. 42

JTAG Interface .................................................................................................................... 45

Block Diagram ..................................................................................................................................... 46

Functional Description ......................................................................................................................... 46

JTAG Interface Pins............................................................................................................................. 47

JTAG TAP Controller ........................................................................................................................... 48

Shift Registers ..................................................................................................................................... 49

Operational Considerations ................................................................................................................. 49

Initialization and Configuration............................................................................................................. 50

Register Descriptions........................................................................................................................... 51

Instruction Register (IR) ....................................................................................................................... 51

Data Registers ..................................................................................................................................... 53

6.1

6.1.1

System Control.................................................................................................................... 55

Functional Description ......................................................................................................................... 55

Device Identification............................................................................................................................. 55

May 4, 2007

Preliminary

Table of Contents

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Reset Control ....................................................................................................................................... 55

Power Control ...................................................................................................................................... 58

Clock Control ....................................................................................................................................... 58

System Control .................................................................................................................................... 60

Initialization and Configuration............................................................................................................. 61

Register Map ....................................................................................................................................... 61

Register Descriptions........................................................................................................................... 62

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

Internal Memory .................................................................................................................. 97

Block Diagram ..................................................................................................................................... 97

Functional Description ......................................................................................................................... 97

SRAM Memory .................................................................................................................................... 97

Flash Memory ...................................................................................................................................... 98

Initialization and Configuration........................................................................................................... 100

Changing Flash Protection Bits ......................................................................................................... 100

Flash Programming ........................................................................................................................... 101

Register Map ..................................................................................................................................... 101

Register Descriptions......................................................................................................................... 102

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

General-Purpose Input/Outputs (GPIOs) ........................................................................ 114

Block Diagram ................................................................................................................................... 115

Functional Description ....................................................................................................................... 115

Data Register Operation .................................................................................................................... 116

Data Direction .................................................................................................................................... 117

Interrupt Operation............................................................................................................................. 117

Mode Control ..................................................................................................................................... 118

Pad Configuration .............................................................................................................................. 118

Identification....................................................................................................................................... 118

Initialization and Configuration........................................................................................................... 118

Register Map ..................................................................................................................................... 120

Register Descriptions......................................................................................................................... 121

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers .................................................................................................. 152

Block Diagram ................................................................................................................................... 153

Functional Description ....................................................................................................................... 153

GPTM Reset Conditions .................................................................................................................... 153

32-Bit Timer Operating Modes........................................................................................................... 153

16-Bit Timer Operating Modes........................................................................................................... 155

Initialization and Configuration........................................................................................................... 159

32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 159

32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 160

16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 160

16-Bit Input Edge Count Mode .......................................................................................................... 160

16-Bit Input Edge Timing Mode ......................................................................................................... 161

16-Bit PWM Mode.............................................................................................................................. 161

Register Map ..................................................................................................................................... 162

Register Descriptions......................................................................................................................... 163

10.

10.1

10.2

10.3

Watchdog Timer ................................................................................................................ 184

Block Diagram ................................................................................................................................... 184

Functional Description ....................................................................................................................... 185

Initialization and Configuration........................................................................................................... 185

Preliminary

May 4, 2007

LM3S317 Data Sheet

10.4

10.5

Register Map ..................................................................................................................................... 185

Register Descriptions......................................................................................................................... 186

11.

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.3.1

11.3.2

11.4

11.5

Analog-to-Digital Converter (ADC) .................................................................................. 207

Block Diagram ................................................................................................................................... 208

Functional Description ....................................................................................................................... 208

Sample Sequencers .......................................................................................................................... 208

Module Control .................................................................................................................................. 209

Hardware Sample Averaging Circuit.................................................................................................. 210

Analog-to-Digital Converter ............................................................................................................... 210

Test Modes ........................................................................................................................................ 210

Internal Temperature Sensor ............................................................................................................. 210

Initialization and Configuration........................................................................................................... 210

Module Initialization ........................................................................................................................... 211

Sample Sequencer Configuration ...................................................................................................... 211

Register Map ..................................................................................................................................... 211

Register Descriptions......................................................................................................................... 212

12.

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.4

12.5

Universal Asynchronous Receiver/Transmitter (UART)................................................ 237

Block Diagram ................................................................................................................................... 238

Functional Description ....................................................................................................................... 238

Transmit/Receive Logic ..................................................................................................................... 238

Baud-Rate Generation ....................................................................................................................... 239

Data Transmission ............................................................................................................................. 240

FIFO Operation .................................................................................................................................. 240

Interrupts............................................................................................................................................ 240

Loopback Operation .......................................................................................................................... 241

Initialization and Configuration........................................................................................................... 241

Register Map ..................................................................................................................................... 242

Register Descriptions......................................................................................................................... 243

13.

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.3

13.4

13.5

Synchronous Serial Interface (SSI) ................................................................................. 273

Block Diagram ................................................................................................................................... 273

Functional Description ....................................................................................................................... 274

Bit Rate Generation ........................................................................................................................... 274

FIFO Operation .................................................................................................................................. 274

Interrupts............................................................................................................................................ 274

Frame Formats .................................................................................................................................. 275

Initialization and Configuration........................................................................................................... 282

Register Map ..................................................................................................................................... 283

Register Descriptions......................................................................................................................... 284

14.

14.1

14.2

14.2.1

14.3

14.4

14.5

Analog Comparator........................................................................................................... 308

Block Diagram ................................................................................................................................... 308

Functional Description ....................................................................................................................... 308

Internal Reference Programming....................................................................................................... 309

Initialization and Configuration........................................................................................................... 310

Register Map ..................................................................................................................................... 311

Register Descriptions......................................................................................................................... 311

15.

15.1

15.2

Pulse Width Modulator (PWM) ......................................................................................... 319

Block Diagram ................................................................................................................................... 319

Functional Description ....................................................................................................................... 319

May 4, 2007

Preliminary

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