P RE L I M I NA R Y
LM3S610 Microcontroller
D A TA SH EET
DS -LM3S 610- 01
C opyr ight © 2006 Lumi nary Micro , Inc.
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Preliminary
October 8, 2006
LM3S610 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 17
About This Document..................................................................................................................... 18
Audience........................................................................................................................................................... 18
About This Manual............................................................................................................................................ 18
Related Documents .......................................................................................................................................... 18
Documentation Conventions............................................................................................................................. 18
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 21
Product Features ................................................................................................................................. 21
Target Applications .............................................................................................................................. 25
High-Level Block Diagram ................................................................................................................... 26
Functional Overview ............................................................................................................................ 27
ARM Cortex™-M3 ............................................................................................................................... 27
Motor Control Peripherals .................................................................................................................... 27
Analog Peripherals .............................................................................................................................. 28
Serial Communications Peripherals..................................................................................................... 28
System Peripherals.............................................................................................................................. 29
Memory Peripherals............................................................................................................................. 30
Additional Features .............................................................................................................................. 30
Hardware Details ................................................................................................................................. 31
System Block Diagram ........................................................................................................................ 32
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 33
Block Diagram ..................................................................................................................................... 34
Functional Description ......................................................................................................................... 34
Serial Wire and JTAG Debug .............................................................................................................. 34
Embedded Trace Macrocell (ETM) ...................................................................................................... 35
Trace Port Interface Unit (TPIU) .......................................................................................................... 35
ROM Table .......................................................................................................................................... 35
Memory Protection Unit (MPU) ............................................................................................................ 35
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 35
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 36
Interrupts ............................................................................................................................. 38
JTAG Interface .................................................................................................................... 41
Block Diagram ..................................................................................................................................... 42
Functional Description ......................................................................................................................... 42
JTAG Interface Pins............................................................................................................................. 43
JTAG TAP Controller ........................................................................................................................... 44
Shift Registers ..................................................................................................................................... 45
Operational Considerations ................................................................................................................. 45
Initialization and Configuration............................................................................................................. 46
Register Descriptions........................................................................................................................... 47
Instruction Register (IR) ....................................................................................................................... 47
Data Registers ..................................................................................................................................... 49
October 8, 2006
Preliminary
3
Table of Contents
6.
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
System Control.................................................................................................................... 51
Functional Description ......................................................................................................................... 51
Device Identification............................................................................................................................. 51
Reset Control ....................................................................................................................................... 51
Power Control ...................................................................................................................................... 54
Clock Control ....................................................................................................................................... 54
System Control .................................................................................................................................... 56
Initialization and Configuration............................................................................................................. 57
Register Map ....................................................................................................................................... 57
Register Descriptions........................................................................................................................... 58
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 93
Block Diagram ..................................................................................................................................... 93
Functional Description ......................................................................................................................... 93
SRAM Memory .................................................................................................................................... 93
Flash Memory ...................................................................................................................................... 94
Initialization and Configuration............................................................................................................. 95
Changing Flash Protection Bits ........................................................................................................... 95
Flash Programming ............................................................................................................................. 96
Register Map ....................................................................................................................................... 96
Register Descriptions........................................................................................................................... 97
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 107
Block Diagram ................................................................................................................................... 108
Functional Description ....................................................................................................................... 109
Data Register Operation .................................................................................................................... 109
Data Direction .................................................................................................................................... 110
Interrupt Operation............................................................................................................................. 110
Mode Control ..................................................................................................................................... 111
Pad Configuration .............................................................................................................................. 111
Identification....................................................................................................................................... 111
Initialization and Configuration........................................................................................................... 111
Register Map ..................................................................................................................................... 113
Register Descriptions......................................................................................................................... 114
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 145
Block Diagram ................................................................................................................................... 146
Functional Description ....................................................................................................................... 146
GPTM Reset Conditions .................................................................................................................... 146
32-Bit Timer Operating Modes........................................................................................................... 146
16-Bit Timer Operating Modes........................................................................................................... 148
Initialization and Configuration........................................................................................................... 152
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 152
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 153
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 153
16-Bit Input Edge Count Mode .......................................................................................................... 153
16-Bit Input Edge Timing Mode ......................................................................................................... 154
16-Bit PWM Mode.............................................................................................................................. 154
Register Map ..................................................................................................................................... 155
Register Descriptions......................................................................................................................... 156
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Preliminary
October 8, 2006
LM3S610 Data Sheet
10.
10.1
10.2
10.3
10.4
10.5
Watchdog Timer ................................................................................................................ 177
Block Diagram ................................................................................................................................... 177
Functional Description ....................................................................................................................... 178
Initialization and Configuration........................................................................................................... 178
Register Map ..................................................................................................................................... 178
Register Descriptions......................................................................................................................... 179
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 200
Block Diagram ................................................................................................................................... 200
Functional Description ....................................................................................................................... 201
Sample Sequencers .......................................................................................................................... 201
Module Control .................................................................................................................................. 202
Hardware Sample Averaging Circuit.................................................................................................. 202
Analog-to-Digital Converter ............................................................................................................... 202
Test Modes ........................................................................................................................................ 202
Internal Temperature Sensor ............................................................................................................. 203
Initialization and Configuration........................................................................................................... 203
Module Initialization ........................................................................................................................... 203
Sample Sequencer Configuration ...................................................................................................... 203
Register Map ..................................................................................................................................... 204
Register Descriptions......................................................................................................................... 205
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 230
Block Diagram ................................................................................................................................... 231
Functional Description ....................................................................................................................... 231
Transmit/Receive Logic ..................................................................................................................... 231
Baud-Rate Generation ....................................................................................................................... 232
Data Transmission ............................................................................................................................. 233
FIFO Operation .................................................................................................................................. 233
Interrupts............................................................................................................................................ 233
Loopback Operation .......................................................................................................................... 234
Initialization and Configuration........................................................................................................... 234
Register Map ..................................................................................................................................... 235
Register Descriptions......................................................................................................................... 236
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 266
Block Diagram ................................................................................................................................... 266
Functional Description ....................................................................................................................... 267
Bit Rate Generation ........................................................................................................................... 267
FIFO Operation .................................................................................................................................. 267
Interrupts............................................................................................................................................ 267
Frame Formats .................................................................................................................................. 268
Initialization and Configuration........................................................................................................... 275
Register Map ..................................................................................................................................... 276
Register Descriptions......................................................................................................................... 277
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
Inter-Integrated Circuit (I2C) Interface ............................................................................ 301
Block Diagram ................................................................................................................................... 301
Functional Description ....................................................................................................................... 301
I
2
C Bus Functional Overview ............................................................................................................. 302
Available Speed Modes ..................................................................................................................... 309
Initialization and Configuration........................................................................................................... 310
Register Map ..................................................................................................................................... 311
October 8, 2006
Preliminary
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