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TSC21020E-25MA

Description
Mixed Signal Processor
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size481KB,37 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

TSC21020E-25MA Overview

Mixed Signal Processor

TSC21020E-25MA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrochip
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
bit size32
FormatFLOATING POINT
JESD-30 codeS-XPGA-P223
JESD-609 codee0
Number of terminals223
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC
encapsulated codePGA
Encapsulate equivalent codePGA223,18X18
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
RAM (number of words)0
Maximum slew rate460 mA
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, MIXED
TSC21020E
Radiation Tolerant 32/40–Bit IEEE Floating–Point
DSP Microprocessor
Introduction
TEMIC Semiconductors is manufacturing a radiation
tolerant version of the Analog Devices ADSP–21020
32/40–Bit Floating–Point DSP.
The product is pin and code compatible with ADI
product, making system development straight forward
and cost effective, using existing development tools and
algorithms.
Features
D
Superscalar IEEE Floating-Point-Processor
D
Off-Chip Harvard Architecture Maximizes Signal Processing
Performance
D
40 ns, 25 MIPS Instruction Rate, Single-Cycle Execution
D
75 MFLOPS Peak, 50 MFLOPS Sustained Performance
D
1024-Point Complex FFT Benchmark : 0.78 ms
D
Divide (y/x) : 240 ns
D
Inverse Square Root (1/√x) : 360 ns
D
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
D
32-Bit Fixed-Point Formats, Integer and Fractional, with
80-Bit Accumulators
D
IEEE Exception Handling with Interrupt on Exception
D
Three Independent Computation Units : Multiplier, ALU,
and Barrel Shifter
D
Dual Data Address Generators with Indirect, Immediate,
Modulo, and Bit Reverse Addressing Modes
D
Two Off-Chip Memory Transfers in Parallel with Instruction
Fetch and Single-Cycle Multiply & ALU Operations
D
Multiply with Add & Subtract for FFT Butterfly
Computation
D
Efficient Program Sequencing with Zero-Overhead
Looping : Single-Cycle Loop Setup
D
Single-Cycle Register File Context Switch
D
15 (or 25) ns External RAM Access Time for
Zero-Wait-State, 40 ns Instruction Execution
D
IEEE JTAG Standard 1149.1 Test Access Port and On-Chip
Emulation Circuitry
D
223 CPGA package for breadboarding
D
256 Multi layer quad flat pack, flat leads, for flight models
D
Full compatible with Analog Devices ADSP-21020
D
Latch up better than 55 MeV
D
Total dose better than 50 Krad (Si)
D
SEU immunity better than 30 MeV/mg/cm
2
– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO
– Product licensed from Analog Devices Inc.
MHS
Rev. D (05 Mai 98)
1
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