LPC1850/30/20/10
32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet,
two High-speed USB, LCD, and external memory controller
Rev. 3 — 6 December 2011
Preliminary data sheet
1. General description
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded
applications. The ARM Cortex-M3 is a next generation core that offers system
enhancements such as low power consumption, enhanced debug features, and a high
level of support block integration.
The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash
Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB
controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog
peripherals.
Remark:
This data sheet describes the Rev ‘-’ and the Rev ‘A’ versions of parts
LPC1850/30/20/10.
2. Features and benefits
Processor core
ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
On-chip memory
200 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access.
64 kB ROM containing boot code and on-chip software drivers.
128 bit One-Time Programmable (OTP) memory for general-purpose use.
Clock generation unit
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC oscillator trimmed to 1 % accuracy over temperature and
voltage.
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
Ultra-low power RTC crystal oscillator.
Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
Clock output.
Configurable digital peripherals:
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like timers, SCT, and ADC0/1.
Serial interfaces:
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 40 MB
per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY. USB interface
electrical test software included in ROM USB stack.
Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support synchronous mode and a smart
card interface conforming to ISO7816 specification.
Two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One Fast-mode Plus I
2
C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I
2
C-bus specification. Supports data rates of up to
1 Mbit/s.
One standard I
2
C-bus interface with monitor mode and standard I/O pins.
Two I
2
S interfaces with DMA support, each with one input and one output.
Digital peripherals:
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
LCD controller with DMA support and a programmable display resolution of up to
1024 H
768 V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
SD/MMC card interface.
Eight-channel General-Purpose DMA (GPDMA) controller can access all memories
on the AHB and all DMA-capable AHB slaves.
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain modes.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to 8 GPIO pins can be selected from all GPIO pins as edge and level sensitive
interrupt sources.
LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 3 — 6 December 2011
2 of 157
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
Four general-purpose timer/counters with capture and match capabilities.
One motor control PWM for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer.
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
Analog peripherals:
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Security:
Hardware-based AES security engine programmable through an on-chip API.
Two 128-bit secure OTP memories for AES key storage and customer use.
Unique ID for each device.
Power:
Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for
the core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available as 208-pin, 144-pin, and 100-pin LQFP packages and as 256-pin, 180-pin,
and 100-pin BGA packages.
3. Applications
Industrial
Consumer
White goods
RFID readers
e-Metering
LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 3 — 6 December 2011
3 of 157
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC1850FET256
LPC1850FET180
LPC1830FET256
LPC1830FET180
LPC1830FET100
LPC1820FET100
LBGA256
Description
Plastic low profile ball grid array package; 256 balls; body 17
17
1 mm
Plastic low profile quad flat package; 208 leads; body 28
28
1.4 mm
Plastic low profile ball grid array package; 256 balls; body 17
17
1 mm
Version
SOT740-2
SOT570-3
SOT459-1
SOT740-2
SOT570-3
SOT486-1
SOT486-1
SOT407-1
SOT486-1
Type number
TFBGA180 Thin fine-pitch ball grid array package; 180 balls
LBGA256
LPC1850FBD208 LQFP208
TFBGA180 Thin fine-pitch ball grid array package; 180 balls
Plastic low profile quad flat package; 144 leads; body 20
20
1.4 mm
Plastic low profile quad flat package; 144 leads; body 20
20
1.4 mm
Plastic low profile quad flat package; 100 leads; body 14
14
1.4 mm
Plastic low profile quad flat package; 144 leads; body 20
20
1.4 mm
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9
9
0.7 mm SOT926-1
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9
9
0.7 mm SOT926-1
LPC1830FBD144 LQFP144
LPC1820FBD144 LQFP144
LPC1820FBD100 LQFP100
LPC1810FET100
LPC1810FBD144 LQFP144
TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9
9
0.7 mm SOT926-1
4.1 Ordering options
Table 2.
Ordering options
Total
SRAM
LCD Ethernet USB0
(Host,
Device,
OTG)
yes
yes
yes
no
no
no
no
no
no
no
no
no
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
no
USB1
ADC
PWM
(Host,
channels
Device)/
ULPI
interface
yes/yes
yes/yes
yes/yes
yes/yes
yes/yes
yes/no
yes/no
no
no
no
no
no
8
8
8
8
8
4
8
4
8
5
4
8
yes
yes
yes
yes
yes
no
yes
no
yes
no
no
yes
QEI
GPIO
Package
Type number
LPC1850FET256 200 kB
LPC1850FET180 200 kB
LPC1850FBD208 200 kB
LPC1830FET256 200 kB
LPC1830FET180 200 kB
LPC1830FET100 200 kB
LPC1830FBD144 200 kB
LPC1820FET100 168 kB
LPC1820FBD144 168 kB
LPC1820FBD100 168 kB
LPC1810FET100 136 kB
LPC1810FBD144 136 kB
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
164
118
142
164
118
49
83
49
83
49
49
83
LBGA256
TFBGA180
LQFP208
LBGA256
TFBGA180
TFBGA100
LQFP144
TFBGA100
LQFP144
LQFP100
TFBGA100
LQFP144
LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 3 — 6 December 2011
4 of 157
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
SWD/TRACE PORT/JTAG
LPC1850/30/20/10
HIGH-SPEED PHY
TEST/DEBUG
INTERFACE
GPDMA
ARM
CORTEX-M3
I-code
bus
BRIDGE 0
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU
GPIO
interrupts
GPIO GROUP0
interrupt
GPIO GROUP1
interrupt
D-code
bus
system
bus
ETHERNET
(1)
10/100
MAC
IEEE 1588
HIGH-
SPEED
USB0
(1)
HOST/
DEVICE/
OTG
USB1
(1)
HOST/
DEVICE
LCD
(1)
SD/
MMC
masters
slaves
AHB MULTILAYER MATRIX
slaves
SPIFI
EMC
64 kB ROM
BRIDGE 1
BRIDGE 2
BRIDGE 3
BRIDGE
BRIDGE
MOTOR
CONTROL
PWM
(1)
I
2
C0
I
2
S0
I
2
S1
C_CAN1
RI TIMER
USART2
USART3
TIMER2
TIMER3
SSP1
I
2
C1
10-bit DAC
C_CAN0
10-bit ADC0
10-bit ADC1
CGU
CCU1
CCU2
RGU
ALARM TIMER
BACKUP REGISTERS
POWER MODE CONTROL
CONFIGURATION
REGISTERS
EVENT ROUTER
OTP MEMORY
64/96 kB LOCAL SRAM
40 kB LOCAL SRAM
16/32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
(1)
AES
HS GPIO
SCT
QEI
(1)
RTC
GIMA
12 MHz IRC
RTC POWER DOMAIN
RTC OSC
= connected to GPDMA
002aaf218
(1) Not available on all parts (see
Table 2).
Fig 1.
LPC1850/30/20/10 block diagram
LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 3 — 6 December 2011
5 of 157
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