ST24C04, ST25C04
ST24W04, ST25W04
4 Kbit Serial I
2
C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x04 versions
– 2.5V to 5.5V for ST25x04 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W04 and ST25W04
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I
2
C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 4 Kbits I
2
C bus
EEPROM products, the ST24/25C04 and the
ST24/25W04. In the text, products are referred to
as ST24/25x04, where "x" is: "C" for Standard
version and "W" for hardware Write Control ver-
sion.
Table 1. Signal Names
PRE
E1-E2
SDA
SCL
MODE
WC
V
CC
V
SS
Write Protect Enable
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
Multibyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
2
E1-E2
PRE
SCL
MODE/WC*
ST24x04
ST25x04
SDA
VSS
AI00851E
Note:
WC signal is only available for ST24/25W04 products.
February 1999
1/16
ST24/25C04, ST24/25W04
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x04
ST25x04
PRE
E1
E2
VSS
1
2
3
4
8
7
6
5
AI00852E
ST24x04
ST25x04
VCC
MODE/WC
SCL
SDA
PRE
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01107E
VCC
MODE/WC
SCL
SDA
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature, Soldering
Input or Output Voltages
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Electrostatic Discharge Voltage (Machine model)
(3)
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
Value
–40 to 125
–65 to 150
215
260
–0.6 to 6.5
–0.3 to 6.5
4000
500
Unit
°C
°C
°C
V
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0
Ω).
DESCRIPTION
(cont’d)
The ST24/25x04 are 4 Kbit electrically erasable
programmable memories (EEPROM), organized
as 2 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
ance of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I
2
C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
2/16
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I
2
C bus defini-
tion. This is used together with 2 chip enable inputs
(E2, E1) so that up to 4 x 4K devices may be
attached to the I
2
C bus and selected individually.
The memories behave as a slave device in the I
2
C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
ST24/25C04, ST24/25W04
Table 3. Device Select Code
Device Code
Bit
Device Select
Note:
The MSB b7 is sent first.
Chip Enable
b4
0
b3
E2
b2
E1
Block
Select
b1
A8
RW
b0
RW
b7
1
b6
0
b5
1
Table 4. Operating Modes
(1)
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Multibyte Write
(2)
Page Write
RW bit
’1’
’0’
’1’
’1’
’0’
’0’
’0’
X
X
V
IH
V
IL
1 to 512
1
4
8
MODE
X
X
Bytes
1
1
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
Notes:
1. X = V
IH
or V
IL
2. Multibyte Write not available in ST24/25W04 versions.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E1 - E2).
These chip enable inputs
are used to set the 2 least significant bits (b2, b3)
of the 7 bit device select code. These inputs may
be driven dynamically or tied to V
CC
or V
SS
to
establish the device select code.
Protect Enable (PRE).
The PRE input pin, in ad-
dition to the status of the Block Address Pointer bit
(b2, location 1FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE).
The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
IL
or V
IH
for the Byte Write
mode, V
IH
for Multibyte Write mode or V
IL
for Page
Write mode. When unconnected, the MODE input
is internally read as V
IH
(Multibyte Write mode).
Write Control (WC).
An hardware Write Control
feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
IH
) or disable (WC =
V
IL
) the internal write protection. When uncon-
nected, the WC input is internally read as V
IL
and
the memory area is not write protected.
3/16
ST24/25C04, ST24/25W04
SIGNAL DESCRIPTIONS
(cont’d)
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x04 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x04 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x04 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x04
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the ST24/25x04
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing.
To start communication be-
tween the bus master and the slave ST24/25x04,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
20
VCC
16
RL
RL
RL max (kΩ)
12
MASTER
8
SDA
SCL
CBUS
CBUS
4
VCC = 5V
0
100
200
CBUS (pF)
300
400
AI01100
4/16
ST24/25C04, ST24/25W04
Table 5. Input Parameters
(1)
(T
A
= 25
°C,
f = 100 kHz )
Symbol
C
IN
C
IN
Z
WCL
Z
WCH
t
LP
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance (ST24/25W04)
WC Input Impedance (ST24/25W04)
Low-pass filter input time constant
(SDA and SCL)
V
IN
≤
0.3 V
CC
V
IN
≥
0.7 V
CC
5
500
100
Test Condition
Min
Max
8
6
20
Unit
pF
pF
kΩ
kΩ
ns
Note:
1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(T
A
= 0 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3V to 5.5V or 2.5V to 5.5V)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (ST24 series)
Supply Current (ST25 series)
Supply Current (Standby)
(ST24 series)
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
SDA in Hi-Z
V
CC
= 5V, f
C
= 100kHz
(Rise/Fall time < 10ns)
V
CC
= 2.5V, f
C
= 100kHz
V
IN
= V
SS
or V
CC
,
V
CC
= 5V
V
IN
= V
SS
or V
CC
,
V
CC
= 5V, f
C
= 100kHz
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V
V
IN
= V
SS
or V
CC
,
V
CC
= 2.5V, f
C
= 100kHz
–0.3
0.7 V
CC
–0.3
V
CC
– 0.5
I
OL
= 3mA, V
CC
= 5V
I
OL
= 2.1mA, V
CC
= 2.5V
Min
Max
±2
±2
2
1
100
300
5
50
0.3 V
CC
V
CC
+ 1
0.5
V
CC
+ 1
0.4
0.4
Unit
µA
µA
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
I
CC
I
CC1
I
CC2
Supply Current (Standby)
(ST25 series)
V
IL
V
IH
V
IL
V
IH
V
OL
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
Input Low Voltage
(E1-E2, PRE, MODE, WC)
Input High Voltage
(E1-E2, PRE, MODE, WC)
Output Low Voltage (ST24 series)
Output Low Voltage (ST25 series)
5/16
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