or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
Lattice Semiconductor
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
sysIO Bank
sysHSI
Block
ispGDX2 Family Data Sheet
sysIO Bank
SERDES
FIFO
GDX Block
SERDES
FIFO
sysHSI
Block
sysHSI
Block
sysCLOCK
PLL
SERDES
FIFO
SERDES
FIFO
GDX Block
sysCLOCK
PLL
sysHSI
Block
GDX Block
GDX Block
GDX Block
GDX Block
SERDES
SERDES
SERDES
SERDES
SERDES
sysHSI
Block
FIFO
FIFO
sysIO Bank
Introduction
The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
sysIO Bank
sysIO Bank
GDX Block
GDX Block
SERDES
sysCLOCK
PLL
FIFO
FIFO
FIFO
FIFO
Global Routing Pool
(GRP)
sysHSI
Block
GDX Block
GDX Block
GDX Block
FIFO
SERDES
GDX Block
GDX Block
SERDES
SERDES
sysHSI
Block
FIFO
FIFO
sysIO Bank
GDX Block
GDX Block
GDX Block
FIFO
SERDES
FIFO
SERDES
FIFO
SERDES
sysHSI
Block
sysCLOCK
PLL
sysIO Bank
sysIO Bank
ISP & Boundary Scan
Test Port
2
Lattice Semiconductor
ispGDX2 Family Data Sheet
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-
bility.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-
pendent of the core voltage supply. This further enhances the flexibility of this family in system designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-
tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface
with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI
Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX
Block can be individually configured in one of four modes:
• Basic (No FIFO or SERDES)
• FIFO Only
• SERDES Only
• SERDES and FIFO
Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard
within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible
with the reference voltage. The banks are independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-
vative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block sup-
plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and
provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility
for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-
nals.
There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by
the software in the allocation of pins.
GDX Block
The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data flow and control logic
for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register
Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
going into and out of a GDX Block.
Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-
put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).
3
Lattice Semiconductor
MUX and Register Block (MRB)
ispGDX2 Family Data Sheet
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be configured as edge-triggered D-type flip-flop or as a level sensitive
latch. One register operates on the input data, the other output data and the last register synchronizes the output
enable function. The input and output data signals can bypass each of their registers. The polarity of the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock
and clock enable. The initialization signals of each register can be independently configured as Set or Reset. These
registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register
input can be set either by one of the two output enables generated locally from the Control Array or from one of the
four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has
access to Global Clock, Clock Enable, Reset and TOE nets.
4
Lattice Semiconductor
Figure 2. GDX Block
GRP
32 bits
MUX
Control Select
8
8
ispGDX2 Family Data Sheet
GDX Block
sysIO Bank
Control Array
Nibble 0
OE
8
2
4 bits
MUX and Register
Block (MRB)
0
IN
OUT
8
2
OE
MUX and Register
Block (MRB)
1
IN
OUT
4 bits
8
2
4 bits
MUX and Register
Block (MRB)
2
OE
IN
OUT
8
OE
2
4 bits
MUX and Register
Block (MRB)
3
IN
OUT
8
2
16 bits
4
8
2
Nibble 1
MRBs 4-7
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
Nibble 2
MRBs 8-11
16 bits
4
8
2
16 bits
4
Nibble 3
MRBs 12-15
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
[align=left][color=#000]I encountered some problems when debugging DMA with MSP432 recently: [/color][/align][align=left][color=#000]1. During debugging, DMA_INT2 and DMA_INT3 interrupts are mapped to...
In the previous two posts, we implemented the LED flashing in different ways. Today, we will implement the LED flashing in the way of semaphore. Two semaphores are used in the program, namely io_sem a...
Why can I erase the blocks of my SST Flash, but not the sectors? What is the reason? I am using SST 39VF6401B. My code: Top[0x555] = 0x00aa; /* Sector Erase Command */ Top[0x2aa] = 0x0055; Top[0x555] ...
This book explains in detail the hardware structure, working principle, resource allocation, functional characteristics and application of each functional module inside the TMS320F28335 DSP processor....
White light LEDs are voltage-sensitive devices. In actual operation, their upper limit is 20mA. However, the current often increases due to various reasons during use. If no protective measures are...[Details]
Amidst the wave of intelligent automotive transformation, advanced driver assistance is gradually emerging from cutting-edge technology into the mainstream, becoming a new frontier of industry comp...[Details]
The Automotive Testing and Quality Assurance Expo (ATE 2025) will open on August 27th. At the expo, Rohde & Schwarz (R&S) will showcase six automotive testing solutions, themed "Intelligently Drivi...[Details]
On August 20th, Tiantai Robotics Co., Ltd., along with strategic partners including Shandong Future Robotics Technology Co., Ltd., Shandong Future Data Technology Co., Ltd., and Gangzai Robotics Gr...[Details]
Permanent magnets are essential components in a wide range of household and industrial devices. They are particularly crucial in the renewable energy sector, including electric vehicle motors. Curr...[Details]
Charging is a familiar process for new energy vehicles, and as a source of battery energy, charging piles are crucial. New energy vehicle charging can be divided into fast charging and slow chargin...[Details]
1. Fault phenomenon and cause analysis
1. During the operation of the equipment, the expansion sleeve is subjected to a large torque, and the mating surfaces of the shaft and the sleeve move...[Details]
During daily operation of an R-type power transformer, the voltage used varies as the equipment being used adjusts. This raises the question: can the transformer change voltage at this point? The a...[Details]
On August 22, the Wall Street Journal reported on the 21st local time that the new US government does not plan to acquire equity in semiconductor wafer foundry giant TSMC and Micron, one of the thr...[Details]
My career has been closely tied to the semiconductor industry. From product management to content marketing, I've provided countless forecasts and predictions across a variety of roles. Whethe...[Details]
In the field of communications power supplies, AC/DC rectifier power supplies are called primary power supplies or basic power supplies, while DC/DC converters are called secondary power supplies. ...[Details]
Inverter power supplies on the market can generally be divided into two categories: sine wave inverters and square wave inverters. Some engineers also like to categorize pure sine wave inverters as...[Details]
Charging is an essential topic for electric vehicles. Batteries are a core component of new energy vehicles. So, what's the optimal charge level for electric vehicles? Based on current battery tech...[Details]
Electric vehicles will revolutionize transportation, changing fuel consumption, carbon emissions, costs, maintenance, and driving habits. Currently, a major selling point for electric vehicles is t...[Details]
From time to time, I see some audiophiles spending a lot of money or a lot of time to DIY speakers, but the results are not what they want. Below I list some of the small experiences I summarized b...[Details]
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
