or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
Lattice Semiconductor
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
sysIO Bank
sysHSI
Block
ispGDX2 Family Data Sheet
sysIO Bank
SERDES
FIFO
GDX Block
SERDES
FIFO
sysHSI
Block
sysHSI
Block
sysCLOCK
PLL
SERDES
FIFO
SERDES
FIFO
GDX Block
sysCLOCK
PLL
sysHSI
Block
GDX Block
GDX Block
GDX Block
GDX Block
SERDES
SERDES
SERDES
SERDES
SERDES
sysHSI
Block
FIFO
FIFO
sysIO Bank
Introduction
The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
sysIO Bank
sysIO Bank
GDX Block
GDX Block
SERDES
sysCLOCK
PLL
FIFO
FIFO
FIFO
FIFO
Global Routing Pool
(GRP)
sysHSI
Block
GDX Block
GDX Block
GDX Block
FIFO
SERDES
GDX Block
GDX Block
SERDES
SERDES
sysHSI
Block
FIFO
FIFO
sysIO Bank
GDX Block
GDX Block
GDX Block
FIFO
SERDES
FIFO
SERDES
FIFO
SERDES
sysHSI
Block
sysCLOCK
PLL
sysIO Bank
sysIO Bank
ISP & Boundary Scan
Test Port
2
Lattice Semiconductor
ispGDX2 Family Data Sheet
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-
bility.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-
pendent of the core voltage supply. This further enhances the flexibility of this family in system designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-
tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface
with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI
Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX
Block can be individually configured in one of four modes:
• Basic (No FIFO or SERDES)
• FIFO Only
• SERDES Only
• SERDES and FIFO
Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard
within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible
with the reference voltage. The banks are independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-
vative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block sup-
plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and
provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility
for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-
nals.
There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by
the software in the allocation of pins.
GDX Block
The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data flow and control logic
for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register
Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
going into and out of a GDX Block.
Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-
put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).
3
Lattice Semiconductor
MUX and Register Block (MRB)
ispGDX2 Family Data Sheet
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be configured as edge-triggered D-type flip-flop or as a level sensitive
latch. One register operates on the input data, the other output data and the last register synchronizes the output
enable function. The input and output data signals can bypass each of their registers. The polarity of the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock
and clock enable. The initialization signals of each register can be independently configured as Set or Reset. These
registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register
input can be set either by one of the two output enables generated locally from the Control Array or from one of the
four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has
access to Global Clock, Clock Enable, Reset and TOE nets.
4
Lattice Semiconductor
Figure 2. GDX Block
GRP
32 bits
MUX
Control Select
8
8
ispGDX2 Family Data Sheet
GDX Block
sysIO Bank
Control Array
Nibble 0
OE
8
2
4 bits
MUX and Register
Block (MRB)
0
IN
OUT
8
2
OE
MUX and Register
Block (MRB)
1
IN
OUT
4 bits
8
2
4 bits
MUX and Register
Block (MRB)
2
OE
IN
OUT
8
OE
2
4 bits
MUX and Register
Block (MRB)
3
IN
OUT
8
2
16 bits
4
8
2
Nibble 1
MRBs 4-7
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
Nibble 2
MRBs 8-11
16 bits
4
8
2
16 bits
4
Nibble 3
MRBs 12-15
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
The LMR24220 module I applied for last time was used in my DIY QQ smart lock. The lock was bought from Taobao. It is a motor-controlled control signal. It is open when 9V is supplied and closed when n...
[size=4][b]About rewards: [/b][/size] [size=4][b]The activity rewards E coins, E coins are equivalent to RMB, which can be used to exchange for physical gifts of your choice. [url=https://bbs.eeworld....
"How to find official documents for STM32 and STM8" This is what you posted in the ST MCU column. I also read the information here. It contains some introductions and chip structures, which can only b...
The Altera 3GPP LTE Turbo Reference Design demonstrates using Turbo codes for encoding with trellis termination support, and forward error correction (FEC) decoding with early termination support. The...
Most of the houses we live in now are elevator buildings, mainly because it is more convenient to go up and down the stairs! It can also make life more comfortable. It even helps to increase the ad...[Details]
To enable real-time monitoring of home security and automatically dial a number for voice prompts or send text messages when an alarm occurs, a GPRS-based embedded telephone alarm system was design...[Details]
Recently,
Xpeng Motors and Xinlian Integrated Circuit jointly announced the mass production of China's first hybrid silicon carbide product.
Designed and developed by Xpeng Motors and joint...[Details]
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[Details]
Recently, AstroBo Robot, a subsidiary of Chenxing Automation, launched a new mobile collaborative palletizing product. Leveraging an omnidirectional mobile chassis, an intelligent scheduling system...[Details]
On August 22, according to the Ministry of Industry and Information Technology's official website, my country's first mandatory national standard for the control of hazardous substances in electric...[Details]
introduction
As “energy conservation and emission reduction” has become an indicator of the National Economic Development Outline of the 11th Five-Year Plan, people’s awareness of green enviro...[Details]
In the scorching summer, electric fans are a must-have for cooling down people's homes. However, I believe most people have encountered this situation: the fan is plugged in, the switch is pressed,...[Details]
Tires are a very important component for cars. They are related to the driving experience of the vehicle. We are almost inseparable from cars in our daily lives. For tires, according to the role of...[Details]
The complexity of the integrated circuits (ICs) used in electronic systems in vehicles is increasing. They aim to execute artificial intelligence (AI) algorithms to control autonomous driving funct...[Details]
Based on the commutation technology, thyristor rectifiers are classified into two main types. Line-commutated and force-commutated inverters are commonly used, while other commutated inverters, nam...[Details]
The 2025 China International Automotive Testing Exhibition will be held at the Shanghai World Expo Exhibition and Convention Center from August 27 to 29, 2025.
Clacton Seafront, UK, ...[Details]
"We have successfully launched the first version of our dedicated chip for EMB brake-by-wire. Second-generation samples have also been successfully completed, and we are actively planning a third-g...[Details]
Speaking of the problem of vehicle spontaneous combustion, whether it is a pure electric vehicle or a fuel vehicle, there will be incidents of spontaneous combustion. For the same spontaneous combu...[Details]
introduction
Inverter air conditioners are a trend in the current era and have gradually become commonplace in countless households. Beyond their basic cooling and heating functions, air condi...[Details]
Embedded System
京公网安备 11010802033920号
EEWORLD
