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M2S080S-VF144Y

Description
SmartFusion2 System-on-Chip FPGAs
File Size7MB,156 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet View All

M2S080S-VF144Y Overview

SmartFusion2 System-on-Chip FPGAs

Revision 0
SmartFusion2 System-on-Chip FPGAs
Microsemi’s SmartFusion
®
2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM
®
Cortex™-M3 processor,
and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most
reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate
count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded
memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an
embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including
controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include
peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +
native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide
high speed memory interfaces.
SmartFusion2 Family
Reliability
Single Event Upset (SEU) Immune
Zero FIT FPGA Configuration Cells
Single Error Correct Double Error Detect (SECDED)
Protection on the Following:
Ethernet Buffers
CAN Message Buffers
Cortex-M3
(eSRAMs)
USB Buffers
PCIe Buffer
DDR Memory Controllers with Optional SECDED
Modes
Embedded
Scratch
Pad
Memory
Enhanced Anti-Tamper Features
Zeroization
Non-Deterministic Random Bit Generator (NRBG)
User Cryptographic Services (AES-256, SHA-256,
Elliptical Curve Cryptographic (ECC) Engine)
User Physically Unclonable Function (PUF) Key
Enrollment and Regeneration
CRI Pass-Through DPA Patent Portfolio License
Hardware Firewalls Protecting
Subsystem (MSS) Memories
Microcontroller
Data Security Features (available on premium devices)
Low Power
Low Static and Dynamic Power
Flash*Freeze Mode for Fabric
< 1 mW in Flash*Freeze Mode
10 mW in Standby Mode
For the M2S050 Device:
Buffers Implemented with SEU Resistant Latches on the
Following:
DDR Bridges (MSS, MDDR, FDDR)
Instruction Cache
MMUART FIFOs
SPI FIFOs
Based on 65 nm Nonvolatile Flash Process
Efficient 4-Input LUTs with Carry Chains for High
Performance and Low Power
Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (x18,
x9, x4, x2, x1)
Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
High Performance DSP Signal Processing
Up to 240 Fast Math Blocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
NVM Integrity Check at Power-Up and On-Demand
No External Configuration Memory Required—Instant-
On, Retains Configuration When Powered Off
Design Security Features (available on all devices)
Intellectual Property (IP) Protection via Unique
Security Features and Use Models New to the PLD
Industry
Encrypted User Key and Bitstream Loading,
Enabling Programming in Less-Trusted Locations
Supply-Chain Assurance Device Certificate
High-Performance FPGA
Security
October 2012
© 2012 Microsemi Corporation
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